New circuit techniques are reported that enable a single VDo SRAM to operate at logic compatible v o h g e s with a cell read current and cell static noise margin (SNM) typically seen with higher/dual VDD SRAMs. Implemented in a 65nm CMOS SO1 process with no alterations to the CMOS process or to a conventional, single VT SRAM cell, the voltage across power rails of the selected S U M cells self-biases to permit a higher-than-VoD voltage during WL active periods and a lower than 2VT voltage at all other times. Bootstrapping the cell row power supply and regulating the cell subarray vimal ground voltage enables the above 'Transregional' SRAM operation resulting in near-subthreshold data storage and superthreshold access, lowering total leakage by over IOX and improving and SNM by 7% and 18% respectively with a total area overhead of less than 13%.Introduction Limited by array leakage and read stability, CMOS SRAM cell device threshold voltages have scaled less aggressively than logic requiring a separate, higher supply VOmELL [1-31 to enable higher SNM and read current and lower read current variability [4-51, in the presence of increasingly severe, random Vr fluctuations in small geometry SRAM cell transistors [6-91. However, a second array power supply translates into more 110 and fewer metal tracks for power, global signal and clock distribution -all of which directly impact cost. Secondly, higheddual cell power supplies result in (i) more leakage due to all components [lo] from unaccessed subarrays of large L2 caches during active mode and (ii) more switching power, adversely impacting battery lifetime for portable applications as well as the cost of packaging for high performance desktop and server products.Bootstrapped Power Lines We propose an alternative to dual power supplies by coupling WL transitions to the cell row power line, PL as shown in Figs 1,2 & 3, to boost the selected cell row power supply voltage only when it is accessed. The stacked PMOS devices in Fig 2 place the shared PL pair of the selected cell row in high impedance during WL active periods and hold them at VOD during all other times. During a read access, the boosted PL does not source any current and merely drives the pull-down cell NFET gate harder, increasing cell beta ratio and cell read current. Since (i) SRAM cells are typically wide and short [3] to enable smaller BL capacitance for a given density and (ii) line-line capacitance/length does not scale down as quickly as parasitic capacitances of cell transistors, the percentage voltage boost on the PL, modeled by (a) in the Appendix, improves with scaling. Also, as a result of (ii) above, charge sharing impact on PL voltage drop for a read access during WL active periods is small, enabling the PL pair to maintain their boosted voltage (Fig 4) while the WL is active. During a write access, when an unstable cell is desirable, the PL sources current to assist the write drivers, collapsing to a few hundred mV (Fig 4) enabling the write drivers to easily flip the cell. The PMOS stack ...
