A design for the monobit-receiver applicationspecific integrated circuit (ASIC) will be described. The monobit receiver is a wide-band (1-GHz) digital receiver designed for electronic-warfare applications. The receiver can process two simultaneous signals and has the potential for fabrication on a single multichip module (MCM). The receiver consists of three major elements: a nonlinear RF front end, a signal sampler and formatting system (analog-to-digital converter (ADC) and demultiplexers), and a patented "monobit" algorithm implemented as an ASIC for signal detection and frequency measurement. The receiver's front end, ADC, and algorithm experimental performance results were previously presented [1]. The receiver uses a 2-b ADC operating at 2.5 GHz whose outputs are collected and formatted by demultiplexers for presentation to the ASIC. The ASIC has two basic functions: to perform a fast Fourier transform (FFT) and to determine the number of signals and report their frequencies. The ASIC design contains five stages: the input, the FFT, the initial sort, the squaring and addition, and the final sort. The chip will process the ADC outputs in real time, reporting detected signal frequencies every 102.4 ns.Index Terms-Analog-to-digital converter (ADC), fast Fourier transform (FFT), instantaneous frequency measurement (IFM) receivers.

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In every computer graphics system, there is some interaction between a special memory called a frame buffer and a computation engine. It is the architecture between these two that determines how fast, flexible, and expensive the graphics subsystem is. In this paper, we present the testability analysis and chip testing of Enhanced Memory Chip (EMC) using the scan-BIST (built-in self-test) partial scan scenario. EMC is a multimillion transistors graphics computation engine produced by WL/AASE, WPAFB in VHDL formats and is fabricated using 0.5 um CMOS technology. Fundamentally, it is memory that is enhanced with tightly-coupled computational logic on the same chip. The logic is arranged in a single instruction, multiple data architecture that can efficiently perform the linear expression evaluation that is common in the lowest level graphic rasterization. The fault simulation shows that partial scan scenario is feasible for EMC and generates scan-BIST high fault coverage and low overhead.