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Through-Silicon-Vias (TSVs) continue to stand out as the most promising technology for electrical interconnections in the microelectronics industry. As package size continues to decrease, TSVs offer an elegant and robust solution for vertical interconnects. They facilitate 3D die stacking while minimizing or even eliminating area consuming planar packaging, allowing for direct signal and power paths through the substrate itself. TSVs can also be fabricated from different materials to desired dimensions to handle the required current level. Plated copper is emerging as the material of choice for TSVs. In this work, electroplated copper TSVs were fabricated successfully and evaluated using cutting and polishing techniques in preparation for image capture. The detailed fabrication process and analysis of the resulting TSVs are presented in this work.

We have designed and tested a piezoresistor for detecting deflection of micromachined Cantilever-In-Cantilever devices making use of the polycrystalline siliconflm of the Mite1 1.5 pm CMOS IC fabrication process. Both static deflection and resonance measurements have been investigated. The change of piezoresistance is about 0.06% under static deflection, which agrees with the ANSYS simulation results. Under dynamic excitation, the piezoresistance AC signal varies linearly with angular deflection of the cantilever, although the variation depends onthe resonance mode. The resonant frequencies of the modes can readily be determined using the piezoresistor.

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