No abstract

No abstract

No abstract

The rapid growth of the wireless local area network (WLAN) market has necessitated new circuit techniques that integrate highpower power amplifiers (PAs), high-sensitivity low-noise amplifiers (LNAs), and RF transmit/receive (T/R) switch components onto a monolithic CMOS IC to alleviate the cost of external discrete components between the system-on-chip (SoC) and the antenna. The popularity of multiple-input multiple-output (MIMO) technologies has further hastened the appeal of these approaches because any external front-end components must be multiplied by the number of RF chains. While solutions exist to integrate an LNA and RF switch with a lower-power PA, the requirements to achieve +20dBm output power on a CMOS SoC often directly contradict the conditions needed for achieving a high sensitivity LNA [1][2][3][4]. This work presents an LNA and RF switch topology that can be integrated together with a +20dBm PA without compromising the LNA performance or reliability and provides independent optimal impedances for both at minimal additional silicon area.The integrated T/R switch must be designed to support the high output power requirements of the PA, while adding minimal insertion loss for both receive and transmit paths. A +20dBm PA requires a low load impedance, high voltage supply, and large supply current. On the other hand, a CMOS LNA requires a higher optimal impedance for minimum noise figure. Inserting an integrated T/R switch using pass transistors allows the LNA and PA to share a common pathway to the antenna, but constrains them to seeing the same impedance. In this design, this incompatibility is overcome by adding a passive π impedance-transformation network in front of the LNA that also functions as the T/R switch, as shown in Fig. 31.4.1. By reusing existing pieces of the PA and LNA circuits for the π network, this RF T/R switch achieves low area usage and low-loss to minimize its impact on the noise figure.Figure 31.4.2 shows the schematic of the LNA, which is a common-gate amplifier that provides up to 20dB of variable gain for the receiver. This topology is chosen for its flexibility in source impedance requirements, while the differential nature of the design increases the robustness of the circuit to package parasitics and common-mode noise. The input of the LNA is connected to the output of the PA by a π transformation network comprised of an inductor L LNA , capacitor C pi , and inductor L PA . In the receive mode, the PA is shut off, and the incoming RF signal from the antenna flows through the π network into the LNA. Since the PA devices are off, it presents a minimal load to the LNA. The π network is configured to achieve the optimal noise figure impedance. The measured LNA S 11 is better than -15dB at 2.4GHz. This LNA, when integrated with an IEEE 802.11g receiver, has an overall receive chain noise figure of 5.8dB. At 1Mb/s data rate, a -94dBm receive sensitivity is achieved. At the more demanding 54Mb/s rate, -73dBm sensitivity is achieved, as shown in Fig. 31.4.3. The LNA draws 8.4...

No abstract