AN EXPERIMENTAL l l n s 8K x 18 SRAM which incorporates advances in processing technology and circuit design will be discussed; Figures I, 2. Problems of making wide-data-path CMOS chips with tolerable noise and difficulties of interfacing next-generation technology chips with current technology have been resolved. The interface voltage levels are full TTL swings. The chip has a 3.6V power supply and uses 0.5pm channel lengths. Numerous parts with all 144K bits operational have been seen. An on-chip test circuit has been implemented t o aid in testing performance accuracy.The experimental fabrication technology is a 1 . 2~ N-well CMOS process with 14nm gate oxides. The nominal channel lengths for both PMOS and NMOS devices are 0.5pm and channel tolerances greater than 0.15pm have been seen while maintaining functionality'. A doubly-implanted lightly-doped drain (DILDD) was employed to minimize Vt rolloff and hotelectron impact o n the time-zero Vt2. A six-device cell with an area of 2 3 5~~ ( 1 3 . 5 p x 17.4pm) was used. The overall chip size was 9.2mm x 6.5mm for a total chip area of 60mm2.The chip has circuit protection to allow input voltage swings to over 5V without damage to the receiver. This was implemented by placing an NMOS pass device in series with the gates of the receiver first stage. The driver is also protected in bidirectional applications; Figure 3 . A self-biasing N-well prevents latchup when the output node is forced higher than 3.6V. The VH supply is similarly gated by the output potential. Therefore, no dc current is drawn into the driver when its output has been tristated. An NMOS pass device is also used t o protect the pulldown circuitry from potentials of 5V or greater. With this design, there is no concern about hot carriers, latchup or snap back.A reference word line serves to provide the internal timing edges for setting the sense-amp latches, in addition to resetting the word-and bitline circuitry. The internal organization has 256word lines and 576-bit line pairs; Figure 4. A double-level word line architecture is employed t o reduce peak current during discharge and restore of the bit lines. An aluminum word line, driven from the center of the chip, contacts 32 sections, 1 6 on each side. Each section has 18b which are directly contacted by a poly-silicon word line which is driven by a section-select driver and the metal word line. Capacitive loading is decreased by acti-Chip operation is triggered by an external chipselect signal. 'Ogura, S., et al., "Submicron MOSFET Performance at Liquid Nitrogen Temperatures", ISSCC D I G E S T OF TECH-N I C A L P A P E R S , P. 160-161: Feb., 1986. 2Hanafi, H.I., "Device Advantages of DI-LDD/LDD MOS-FET over DD MOSFET". I E E E Circuits and Deuices, p. 13-15: Nov., 1985.vating only one section. All bit lines and data lines are precharged to full Vh prior t o read or write operation. Separate read and write bit switches are employed at each end of the bit lines to reduce capacitance in the data out path. NMOS devices are used for discharging bi...

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