Lightweight, flexible solar cells from III−V semiconductors offer new application opportunities for devices that require a power supply, such as cars, drones, satellites, or wearable devices, due to their outstanding efficiency and power-to-weight ratio (specific power). However, the specific power and stability of flexible photovoltaic (PV) devices need to be enhanced for use in such applications because current flexible PV devices are vulnerable to moisture and heat. Here, we develop ultra-lightweight, flexible InGaP/GaAs tandem solar cells with a dual-function encapsulation layer that serves as both a moisture barrier and an antireflection coating for the active device layer. Using a thin polymer film as a substrate and an ultrathin metal as a bonding layer, the total weight of the device is dramatically reduced. Therefore, the specific power of our solar cells is remarkably high with a value of over 5000 W/kg under the AM 1.5G solar spectrum. Additionally, there is no degradation even if the solar cells are exposed to harsh environmental conditions.

Although they have attracted enormous attention in recent years, software-based and two-dimensional hardware-based artificial neural networks (ANNs) may consume a great deal of power. Because there will be numerous data transmissions through a long interconnection for learning, power consumption in the interconnect will be an inevitable problem for low-power computing. Therefore, we suggest and report 3D stackable synaptic transistors for 3D ANNs, which would be the strongest candidate in future computing systems by minimizing power consumption in the interconnection. To overcome the problems of enormous power consumption, it might be necessary to introduce a 3D stackable ANN platform. With this structure, short vertical interconnection can be realized between the top and bottom devices, and the integration density can be significantly increased for integrating numerous neuromorphic devices. In this paper, we suggest and show the feasibility of monolithic 3D integration of synaptic devices using the channel layer transfer method through a wafer bonding technique. Using a low-temperature processible III–V and composite oxide (Al2O3/HfO2/Al2O3)-based weight storage layer, we successfully demonstrated synaptic transistors showing good linearity (αp/αd = 1.8/0.5), a high transconductance ratio (6300), and very good stability. High learning accuracy of 97% was obtained in the training of 1 million MNIST images based on the device characteristics.