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Semiconductor industry has been experiencing rapid and continuous shrinkage of feature size along with Moore's law. As the VLSI technology scales down to sub 40nm process node. Control of critical dimension (CD) and Extraction of Unanticipated weak point pattern effects known as "hot spots" becoming more challenging and difficult. Therefore, experimental full-chip inspection methodologies for Control of critical dimension (CD) and hotspots extraction are necessary in order to reduce Turn-Around-Time (TAT) for steep ramp up Manufacture. In this paper, we introduce the concepts of an innovative reduction Turn-around-time (TAT) in manufacture production with applications of DBV (Design Based Verification). The noble methodologies employed by our own technology with application of DBV are highly advantageous for exactly determining for process judgment go or no-go about wafer process in mass-production of memory device.

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