This article presents a three-phase two-level impedance-source inverter to decrease the magnitude of common-mode voltage and enhance the output voltage capability. Shoot-through states are inserted into zero states to ensure for boosting voltage and improving the output voltage quality with higher modulation index. Moreover, the advantage of the proposed solution is as low voltage stress on capacitors, switches and diodes in impedance-source network. The theoretical analysis, circuit analysis, and logic functions of the proposed solution are introduced. A comparison between the proposed solution with other impedance-source inverter topologies for common-mode voltage reduction is also reported. Besides that, the simulation verification and 1-kW experimental prototype were developed and verified to prove the proposed solution.

In this article, a novel single-stage transformerless buck–boost inverter is introduced. The proposed inverter can share a common ground between the DC input side and the grid; this leads to having a zero-leakage current. The proposed inverter also provides the buck and boost voltage capabilities. Additionally, the power switches are operated at high frequency in the half-cycle of the sinusoidal wave, so the efficiency of the proposed inverter can be improved. Operating analysis, design consideration, comparison, and simulation study are presented. Finally, a 500 W laboratory prototype is also built to confirm the correctness and feasibility of the proposed inverter.

A novel single-phase nine-level boost inverter is proposed in this paper. The proposed inverter has an output voltage which is higher than the input voltage by switching capacitors in series and in parallel. The maximum output voltage of the proposed inverter is determined by using the boost converter circuit, which has been integrated into the circuit. The proposed topology is able to invert the multilevel voltage with the high step-up output voltage, simple structure and fewer power switches. In this paper, the circuit configuration, the operating principle, and the output voltage expression have been derived. The proposed converter has been verified by simulation and experiment with the help of PSIM software and a laboratory prototype. The experimental results match the theoretical calculation and the simulation results. IntroductionRecently, multilevel inverters (MIs) have played important roles for high-power applications because of their advantages as better output voltage waveforms quality, a reduced rating of power semiconductor devices, and low electromagnetic interference [1]. The traditional MI topologies are neutral-point-clamped (NPC), flying-capacitor (FC), and cascade H-Bridge (CHB) inverters [2][3][4][5]. Diodes and capacitors are used to generate multilevel at the output voltage in NPC and FC inverters, respectively. On the other hand, to attain voltage levels, the direct current (DC) source must be increased. Nevertheless, both the circuit configurations and their controls become very complicated along with the increasing number of the output voltage levels. Furthermore, these topologies also make capacitors' imbalanced. Some in-depth studies for NPC's topologies have been presented in References [6][7][8]. To operate at the higher voltage level, the CHB inverters are used thanks to easy modularization and facilitate to expansion extension [9,10]. However, the topologies request more and more power devices with separate DC voltage sources. When the output voltage has more levels, the number of the required input DC sources is increased. Construction of a multilevel converter was introduced in Reference [11] with the use of multiple modules that made it easy to expand. However, this also increases the number of capacitors and switches required.A seven-level inverter using series-connected DC voltage sources was presented in Reference [12] with the use of multiple DC voltage sources supplies to reduce switching losses. However, the number of output voltage levels depends on the number of DC voltage sources. A circuit of (4n + 3)-level inverter using voltage sources in serial/parallel operation was introduced in Reference [13] to increase the number of output voltage levels with the complex pattern and increase the conductive losses. By using an additional boost converter to create a multi-step output with capacitors, a seven-level

In grid-connected photovoltaic (PV) systems, a transformer is needed to achieve the galvanic isolation and voltage ratio transformations. Nevertheless, these traditional configurations of transformers increase the weight, size, and cost of the inverter while decreasing the efficiency and power density. The transformerless topologies have become a good solution. However, the problem is that commode-mode voltage and leakage current can occur via the stray capacitors between the PV array and the ground of the inverter. Various transformerless inverters have been introduced with different techniques, such as reducing the common-mode voltage or eliminating the leakage current. Furthermore, to introduce the development of transformerless PV inverters, especially in three-phase two-level inverter systems, this paper provides a comprehensive review of various common-mode voltage reduction three-phase two-level inverters.

This paper proposes a single-phase, single-stage common-ground inverter with a non-electrolytic capacitor and buck-boost ability. The proposed single-stage inverter is employed by a boost stage DC-DC converter and bimodal circuit, which makes it satisfactory for PV systems with a wide input voltage range and lower switch voltage stress. The leakage current of the proposed single-stage inverter can effectively suppress because the parasitic capacitor between the PV panel and the ground is shortened. In addition, the proposed single-stage inverter does not include electrolytic capacitors, which reduces the equivalent series resistance of electrolytic capacitors and also the size of the inverter system. The topology, operating principle, and PWM control method of the proposed single-stage inverter are given. The design guidelines of components and comparative studies of the proposed single-stage inverter are provided. A 500 W laboratory prototype of the proposed single-stage inverter is built to verify the correctness of the simulation and theoretical analysis.