Design methodology for nonvolatile SRAM (NV-SRAM) using magnetic tunnel junctions (MTJs) and architectures for improving its energy efficiency are investigated. The cell is comprised of an ordinary 6T-SRAM cell and MTJs connected to its storage nodes through additional pass transistors that enable it to electrically separate the MTJs from the 6T cell part during the normal SRAM operation mode. From the viewpoints of the stabilities (noise margins) of all the operation modes and the store currents to the MTJs with careful consideration for device process variability, the design methodology is developed. The energy efficiency is dramatically enhanced by reducing leakage currents during the normal SRAM operation and shutdown modes and by optimizing store energy to the MTJs. A newly introduced hierarchical store-free (HSF) architecture is also highly effective at improving the energy efficiency. The energy performance is computationally analyzed and experimentally verified using circuit parameters extracted from fabricated test-element-group circuits of the NV-SRAM.

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A store energy and latency reduction architecture based on proactive useless data flush (PUDF) is proposed for nonvolatile SRAM (NV-SRAM) using magnetic tunnel junctions (MTJs). Prior to the store operation to the MTJs in the array, the PUDF architecture predicts storeunneeded blocks having useless data and shuts down these blocks in advance. As a result, the store energy and latency can be reduced depending on the proportion of store-unneeded blocks, which enhances the energy reduction efficiency of power gating (PG) using the NV-SRAM. The energy and latency characteristics are computationally analysed and experimentally verified using circuit parameters extracted from fabricated test-element-group (TEG) circuits of the NV-SRAM.