Design and Performance of Virtually Nonvolatile Retention Flip-Flop Using Dual-Mode Inverters

Kitagata, Daiki; Yamamoto, S.; Sugahara, Satoshi

doi:10.1109/ngcas.2018.8572109

Cited by 2 publications

(6 citation statements)

References 6 publications

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“…As the circuit is only clock gated not power gated during standby periods, there is reduction in only dynamic power dissipation. Whereas, Kitagata et al (2018) and Kobayashi and Enomoto (2019) use the power gating (PG) technique to reduce the static power dissipation and dynamic power dissipation during the standby mode. To prevent the loss of state during the standby mode, Kitagata et al (2018) proposed a retentive FF that has dual-mode inverters that act as Schmitt trigger inverter during the standby mode and conventional inverter during the normal/active mode.…”

Section: Simulation Resultsmentioning

confidence: 99%

“…Whereas, Kitagata et al (2018) and Kobayashi and Enomoto (2019) use the power gating (PG) technique to reduce the static power dissipation and dynamic power dissipation during the standby mode. To prevent the loss of state during the standby mode, Kitagata et al (2018) proposed a retentive FF that has dual-mode inverters that act as Schmitt trigger inverter during the standby mode and conventional inverter during the normal/active mode. Whereas, Kobayashi and Enomoto (2019) use the low-voltage retentive operation mode during the standby mode.…”

Section: Simulation Resultsmentioning

confidence: 99%

“…In-place state retention eliminates the overhead associated with data movement by substituting conventional flip-flop with a state-retentive flip-flop (SRFF), which ensures quick wakeup by reducing restoration time. In a conventional SRFF, data is preserved by additional data retention circuitry, while rest of the circuit is powered down to achieve lower power consumption (Shigematsu et al , 1997; Mutoh et al , 1996; Kobayashi and Enomoto, 2019; Moreau et al , 2019; Kitagata et al , 2018; Jiao and Kursun, 2010). “Always ON” data retention circuitry still contributes to power dissipation, which can be eliminated by integrating non-volatile memory element with a complementary metal–oxide semiconductor (CMOS).…”

Section: Introductionmentioning

confidence: 99%

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Energy-efficient data retention in D flip-flops using STT-MTJ

Monga

Chaturvedi

Gurunarayanan

2020

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Purpose Emerging event-driven applications such as the internet-of-things requires an ultra-low power operation to prolong battery life. Shutting down non-functional block during standby mode is an efficient way to save power. However, it results in a loss of system state, and a considerable amount of energy is required to restore the system state. Conventional state retentive flip-flops have an “Always ON” circuitry, which results in large leakage power consumption, especially during long standby periods. Therefore, this paper aims to explore the emerging non-volatile memory element spin transfer torque-magnetic tunnel junction (STT-MTJ) as one the prospective candidate to obtain a low-power solution to state retention. Design/methodology/approach The conventional D flip-flop is modified by using STT-MTJ to incorporate non-volatility in slave latch. Two novel designs are proposed in this paper, which can store the data of a flip-flip into the MTJs before power off and restores after power on to resume the operation from pre-standby state. Findings A comparison of the proposed design with the conventional state retentive flip-flop shows 100 per cent reduction in leakage power during standby mode with 66-69 per cent active power and 55-64 per cent delay overhead. Also, a comparison with existing MTJ-based non-volatile flip-flop shows a reduction in energy consumption and area overhead. Furthermore, use of a fully depleted-silicon on insulator and fin field-effect transistor substituting a complementary metal oxide semiconductor results in 70-80 per cent reduction in the total power consumption. Originality/value Two novel state-retentive D flip-flops using STT-MTJ are proposed in this paper, which aims to obtain zero leakage power during standby mode.

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Section: Simulation Resultsmentioning

confidence: 99%

Section: Simulation Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Energy-efficient data retention in D flip-flops using STT-MTJ

Monga

Chaturvedi

Gurunarayanan

2020

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“…In the prior art there are two approaches to achieve a low leakage flip-flop (FF) with data retention capability 1) nonvolatile data retention FF (NV-FF) [1], [2], [3], [4], [5], [6], [7], [8], [9], [10] and 2) CMOS FF with a balloon latch (DR-FF). The NV-FF allows zero power consumption to maintain the data during the sleep mode, whereas the DR-FF requires an always-on circuity to preserve the data [11], [12], [13], [14], [15], [16]. Nevertheless, NV-FFs have several disadvantages over CMOS DR-FFs, particularly for duty-cycled systems with short and frequent sleep modes.…”

Section: Introductionmentioning

confidence: 99%

“…In prior work, various DR-FFs have been proposed to reduce the sleep mode leakage power consumption. In [11], a DR-FF is proposed which can be configured as a Schmitt-trigger inverter and as a regular inverter during sleep and active mode, respectively. This design enables data retention down to 0.2 V with 220 pW sleep mode power consumption.…”

Section: Introductionmentioning

confidence: 99%

A 380 fW Leakage Data Retention Flip-Flop for Short Sleep Periods

Sedighiani

Singh

Jordans

et al. 2023

IEEE Trans. Circuits Syst. II

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Design and Performance of Virtually Nonvolatile Retention Flip-Flop Using Dual-Mode Inverters

Cited by 2 publications

References 6 publications

Energy-efficient data retention in D flip-flops using STT-MTJ

Energy-efficient data retention in D flip-flops using STT-MTJ

A 380 fW Leakage Data Retention Flip-Flop for Short Sleep Periods

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