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A new voltage reference circuit based only on MOS and vertical substrate PNP transistors is described. The circuit designed in 130 nm CMOS standard process operates in the temperature range [-40… +125] ºC with supply voltages from 2.0 V to 3.0 V. It consumes 600 nA at 2.5 V and 27ºC in the typical corner and occupies 0.0063 mm 2 area. The reference voltage is 1.0094 V ±35µV from 0ºC to 100ºC at 2.5V supply in the typical corner. A line sensitivity of 245 µV/V in the supply voltage range [2.25… 3.0] V is achieved. The power supply rejection ratio at 10 Hz is -71 dB.

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