Edge detection is one of the most important steps in image processing and pattern recognition, it is also a critical technology of hand bone identification. Canny edge detection algorithm is simple, easy to implement and fast execution advantage, therefore, it still maintain a certain degree of competitiveness in the practical application. Firstly, the principles and the existing problems of Canny algorithm are studied in this paper, against threshold problem, improved method of an adaptive threshold is proposed, using Otsu method selected threshold, the split results would be better. Finally, the experimental results show that the proposed method can effectively extract the edge of the images.

By adjusting a variety of different frequency signals, equalizer compensates or optimizes system deficiencies, equalizer is used in voice, communication systems, mechanical vibration, fault diagnosis and many other fields. Traditional analog equalizer has low precision, phase nonlinearity and more distortion characteristics. On the basis of this, a new digital equalization algorithm that abandon the traditional single FIR filter implementation method is proposed, frequency division effect is achieved by multiple phase sub-band filter row and multi-channel digital potentiometer, so the cost of digital equalizer design and difficulty of implementation are reduced, and flexibility of digital equalizer settings on the real-time system is improved. In this paper, QuartusII is applied to functional simulation, and downloaded into the FPGA via JTAG interface to verify the correctness of the results.

Addition is the most frequent floating point operation in modern microprocessors. The design of floating point addition is relatively complex than other flotation point arithmetic operations. Due to its complex shift-add-shift-round data flow, floating point addition can have a long latency. This paper has shown an efficient implementation of addition module on a reconfigurable platform cyclone IV EP4CE15, which is both area as well as performance optimal. The proposed design has optimized the individual complex components of adder module (like dynamic shifter, leading one detector (LOD), priority encoder), to achieve the better overall implementation. Comparison with the best reported.

SOPC technology of Nios II is Used for the design of intelligent digital photo frame in this paper. Developers can integrate design according to actual needs, fundamentally changing the lack of traditional design. Digital photo frame as a whole project is divided into two parts of the hardware module and software system. Functional correctness is verified by Quartus II, further downloaded to the FPGA for debugging, the observation results showed that digital photo frame has a high degree of freedom in the system optimization, which can be extended the life of the product on the market, greatly improving the performance of multi-function digital photo frame.