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The watershed transformation is a popular image segmentation technique for gray scale images. This paper describes a real-time image segmentation based on a parallel and pipelined watershed algorithm which is designed for hardware implementation. In our algorithm:(1) pixels in a given image are repeatedly scanned from top-left to bottom-right, and then from bottom-right to topleft, in order to achieve high performance on a pipelined circuit by simplifying memory access sequences, (2) all steps in the algorithm are executed at the same time in the pipelined circuit, (3) the amount of data that are scanned is gradually reduced as the calculation progresses by memorizing which data are modified in the previous scan, and (4) N pixels can be processed in parallel. In our current implementation on an off-the-shelf field-programmable gate array board, up to four pixels can be processed in parallel. The performance for 512 9 512 pixel images is fast enough to be the first step in real-time applications.

Image segmentation is one of the most important tasks in the image processing, and mean shift algorithm is often used for color image segmentation because of its high quality. The computational cost of the mean shift algorithm, however, is high, and it is difficult to realize its real time processing on microprocessors, though many techniques for reducing the cost have been researched. In this paper, we describe an FPGA system for the image segmentation based on the mean shift algorithm. In the image segmentation based on the mean shift algorithm, the image is once over-segmented, and then the small regions are merged considering the similarity between the over-segmented regions in order to obtain better segmentation. In our system, the mean shift filter is accelerated using a cache memory which can access to all pixels in a w s × w s pixel window at arbitrary position. This cache memory allows us to process w s × w s pixels in parallel every clock cycle. The region merging is also accelerated by not strictly managing the list structures used for the merging. This loose management introduces the redundant and out-of-date data into the list structures, but it makes the pointer dereferences unnecessary, and the overhead by those data can be hidden by pipeline processing. The performance for 768 × 512 pixel images is fast enough for real-time applications.

No abstract

The watershed transformation is a popular image segmentation technique for grey scale images. This paper describes a pipeline implementation of a watershed algorithm designed for hardware implementation. In the algorithm, pixels in a given image are repeatedly scanned from top-left to bottomright, and then from bottom-right to top-left in order to propagate the value of each pixel to its neighbors. In the implementation, w-sets of k-lines are buffered on the FPGA, and the algorithm is repeatedly applied to w-sets, shifting in a new set from the external memory banks and shifting out the oldest set to other external memory banks. w and k can be chosen according to the number of the external memory banks and the size of the FPGA. Therefore, it is possible to realize the best performance on a given hardware platform.