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Purpose Full adder cells are building blocks of arithmetic circuits and affect the performance of the entire digital system. The purpose of this study is to provide a low-power and high-performance full adder cell. Design/methodology/approach Approximate computing is a novel paradigm that is used to design low-power and high-performance circuits. In this paper, a novel 1-bit approximate full adder cell is presented using the combination of complementary metal-oxide-semiconductor, transmission gate and pass transistor logic styles. Findings Simulation results confirm the superiority of the proposed design in terms of power consumption and power–delay product (PDP) criteria compared to state-of-the-art circuits. Also, the proposed full adder cell is applied in an 8-bit ripple carry adder to accomplish image processing applications including image blending, motion detection and edge detection. The results confirm that the proposed cell has premier compromise and outperforms its counterparts. Originality/value The proposed cell consists of only 11 transistors and decreases the switching activity remarkably. Therefore, it is a low-power and low-PDP cell.