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Signal return path discontinuities, parasitic inductance and impedance mismatch within interconnects are major factors that contribute to degraded high-speed signal quality in threedimensional (3D) integrated circuits and systems. In this paper, we apply an alternate power delivery method and a novel I/O signaling scheme to a 3D system to address these issues. Two test vehicles made of stacked PCBs that resemble 3D integrated systems will be presented. One test vehicle is designed based on our proposed approach while the other is based on the conventional power delivery network design. The signal integrity and power supply noise performance will be shown in both simulated environment and actual test measurement. At data rates up to 3Gbps, our proposed design produces higher signal quality than the conventional design with better eye height, lower timing jitter, and lower power supply noise.