New power delivery scheme for 3D ICs to minimize simultaneous switching noise for high speed I/Os

Zhang, David C.; Swaminathan, Madhavan; Huh, Suzanne

doi:10.1109/epeps.2012.6457849

Cited by 8 publications

(12 citation statements)

References 7 publications

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“…The PTL design concept was then applied to 3D models and produced optimistic results in the previously published work in [4] and [9]. The simulated result showed the SI and PI performances of our proposed method clearly exceed that of the traditional design in a 3D system.…”

Section: Fig 3 Power Transmission Line Based Pdn In a Pcbmentioning

confidence: 51%

“…The parasitic inductance between adjacent stacked dies in our previously presented simulation model [4] was about 66.9pH. Therefore, the inductance between two stacked PCBs in the TVs is approximately 116 times more than the parasitic inductance from the simulation model presented in [4]. We will show through measurement that even with this large parasitic inductance we can still maintain good SI and PI with our proposed PTL based design with minimum number of decoupling capacitors.…”

Section: D Pcb Test Vehicle Informationmentioning

confidence: 83%

“…The inductance of each connection within the board-board connector is estimated to be 7.77nH between adjacent PCBs. The parasitic inductance between adjacent stacked dies in our previously presented simulation model [4] was about 66.9pH. Therefore, the inductance between two stacked PCBs in the TVs is approximately 116 times more than the parasitic inductance from the simulation model presented in [4].…”

Section: D Pcb Test Vehicle Informationmentioning

confidence: 94%

“…As illustrated in [3] and [4], due to increasing parasitic inductance from interconnects among the stacked dies, the impedance of the PDN of a higher die is more than that of a lower die in the inductive region. Consequently this increasing parasitic inductance contributes to higher simultaneous switching noise (SSN) as one moves up the stack.…”

Section: Fig 2 Illustration Of Rpd Cause-effect In a Pcbmentioning

confidence: 98%

“…Therefore current fluctuation or di/dt is minimized [1] and [2]. With a minimum di/dt, even we have significant parasitic inductance along the path of PDN in a 3D structure; noise can be kept at a minimum [4]. …”

Section: Proposed Ptl-based Designmentioning

confidence: 98%

See 4 more Smart Citations

Characterization of alternate power distribution methods for 3D integration

Zhang

Swaminathan

Keezer

et al. 2014

2014 IEEE 64th Electronic Components and Technology Conference (ECTC)

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Signal return path discontinuities, parasitic inductance and impedance mismatch within interconnects are major factors that contribute to degraded high-speed signal quality in threedimensional (3D) integrated circuits and systems. In this paper, we apply an alternate power delivery method and a novel I/O signaling scheme to a 3D system to address these issues. Two test vehicles made of stacked PCBs that resemble 3D integrated systems will be presented. One test vehicle is designed based on our proposed approach while the other is based on the conventional power delivery network design. The signal integrity and power supply noise performance will be shown in both simulated environment and actual test measurement. At data rates up to 3Gbps, our proposed design produces higher signal quality than the conventional design with better eye height, lower timing jitter, and lower power supply noise.

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Section: Fig 3 Power Transmission Line Based Pdn In a Pcbmentioning

confidence: 51%

Section: D Pcb Test Vehicle Informationmentioning

confidence: 83%

Section: D Pcb Test Vehicle Informationmentioning

confidence: 94%

Section: Fig 2 Illustration Of Rpd Cause-effect In a Pcbmentioning

confidence: 98%

Section: Proposed Ptl-based Designmentioning

confidence: 98%

See 3 more Smart Citations

Characterization of alternate power distribution methods for 3D integration

Zhang

Swaminathan

Keezer

et al. 2014

2014 IEEE 64th Electronic Components and Technology Conference (ECTC)

Self Cite

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show abstract

High-speed packages with imperfect power and ground planes

Liu¹,

Frye²,

Hlaing

et al. 2013

2013 IEEE 63rd Electronic Components and Technology Conference

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Power distribution network design optimization with on-die voltage-dependent leakage path

Zhang

Liu

Coutts

et al. 2013

2013 IEEE 22nd Conference on Electrical Performance of Electronic Packaging and Systems

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Leakage current has become a significant source of power consumptions of CMOS circuit, as the technology node continues to shrink. Our study shows that the equivalent on-die leakage resistance monotonically decreases as the supply voltage increases and exceeds MOSFET threshold voltage. We propose a system-level power distribution network (PDN) design optimization with voltage-dependent leakage resistance considered in a standard RLC tank model. Our results show that the voltagedependent leakage resistance can impact on the PDN noise and affect the optimal value of the circuit parameters to minimize the noise. An equivalent constant leakage resistor is proposed to replace the voltage-dependent model for quick noise prediction.

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New power delivery scheme for 3D ICs to minimize simultaneous switching noise for high speed I/Os

Cited by 8 publications

References 7 publications

Characterization of alternate power distribution methods for 3D integration

Characterization of alternate power distribution methods for 3D integration

High-speed packages with imperfect power and ground planes

Power distribution network design optimization with on-die voltage-dependent leakage path

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