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In this paper, a 2-layer eWLB (embedded Wafer-Level BGA) is studied and its performance is compared with an equivalent 4-layer laminate package. Since eWLB package is processed by using lithographical method, design rules on width (W) and spacing (S) are much finer (usually 2–3 times finer) than those for laminate package. In other words, signal traces can be implemented in smaller fan-out regions. The smaller feature sizes for signal traces would end up with more metal loss per unit length. But as the signal traces can be implemented in smaller fan-out regions, overall trace-routing may be shorter, and equivalent insertion-loss may be achieved. In eWLB, the ground plane is closer to the signal traces. This actually helps to reduce cross-talk between wide I/O buses, as the electrical field is contained in a smaller region by the closer ground plane. Another key advantage from wafer-level package is a smoother metal surface, which greatly reduces the extra signal loss, due to surface-roughness effect, especially for higher-frequency and higher-speed applications. In addition, through-via structures for wafer-level package are typically 2–3 times smaller. This allows to implement power/ground planes in a more continuous way, achieving better resistance and inductance for power/ground nets. Overall electrical performance, which takes into account of all the impacts above, can be evaluated by signal-integrity analysis (E-diagram). Measurement data of a 2-layer eWLB package for a LPDDR application will be presented, which shows the comparable performance typically obtained from a 4-layer laminate package

In this paper, we present some passive components made from silicon substrate technology (Integrated Passive Device process) and integration schemes using these components for RF applications. RF decoupling capacitors from this process are characterized on ESR and ESL performance. Functional blocks (filters, baluns, diplexers, matching, etc) made from the IPD process, have shown good electrical performance with small form-factor features. The thin profiles from the IPDs make them very suitable to be used inside laminate and QFN packages. System-in-Packages or multiple-chip-modules using IPD approaches may have significant size reduction. The low profiles and the small form-factors of the IPDs result in less cross-talk between the IPDs and their nearby components (chips, SMDs, and routing traces, etc), and therefore it is easier to maintain signal integrity for packages.

Wafer-level packages, such as embedded-Wafer-Level-Ball-Grid-Array (eWLB) packages, can provide smaller form-factors and thinner profiles, as finer design rules on W/S, and thinner layers (both metal layers and passivation layers) can be applied in such packages. However, a routine conversion from fcBGA to eWLB does not guarantee the electrical performance will be the same. Designer's electrical skills still play important roles to reduce design cycle-time for meeting critical electrical performance. We compare the performance from typical fcBGA and eWLB packages in the following areas: insertion-loss for signal nets, power-ground impedance for P/G nets, and cross-talk for both signal nets and P/G nets. Simulation data for both fcBGA and eWLB, along with some experimental data, is provides in the paper. As metal-layer thickness (4um-12um) in eWLB is typically smaller, and finer design rules are used, the cross-section of a signal trace is smaller, which translates a higher metal-loss in unit- length. In addition, as the passivation layers in eWLB have slightly worse loss-tangent properties, it's substrate-loss is also little higher. The overall aspects above result in higher transmission-line (TML) loss in eWLB in unit-length. But as shorter trace-routing is possible in eWLB, given finer design rules, the overall transmission-line loss could be equivalent to that of a fcBGA transmission-line. The finer design rules on vias in eWLB facilitate to implement Power/Ground (P/G) planes in a more continuous way, and contribute to less P/G impedance. In addition, as the layer-to-layer separation is smaller, decoupling capacitance inheritably made between the P/G planes is larger, which eventually helps to provide a better or smaller P/G loop-impedance. Because of less separation distance between metal layers in eWLB, the signal traces see much closer GND planes (e.g., 5um in eWLB versus 50um in fcBGA) in their proximities. The closer GND planes make the electrical fields more locally contained. As a result, in a typical eWLB design (e.g., 12um/12um for L/S), the cross-talk between DDR data buses is typically smaller than that from a fcBGA design (e.g., 30um/30um for L/S).