This research was performed to address the issue of shock robustness in silicon microstructures. The improvements were incorporated by considering features to reduce stress concentration and by geometries that have a more uniform stress distribution. The designs were evaluated by finite element models and by testing with wafer level techniques. The designs were intended to have the same fundamental frequency, inertia properties and damping properties. Six different designs were developed and distributed across 900 die on multiple 4-inch wafers. The wafers were subjected to repeated shocks at magnitudes of 130, 2008, and 3680 gs with a 0.25 msec duration.Automated optical inspection was used to interrogate each die and determine which test structures survived the shock test. Subsequent to testing, analysis of variance was used to identify the significant factors that influence the failure rate. This analysis has shown beam design, wafer orientation, acceleration level, and the interactions of beam design*wafer orientation, wafer orientation*acceleration level to be significant factors contributing to the failure rate. The designs were grouped according to mean failure rate. The "small bow tie" design had the highest failure rate and was a separate population. Its failure rate was two to four times that of other designs. The second grouping of lower failure rates included all designs to address the stress concentration. Of these designs, the "no gusset" design has the highest failure rate (twice that of other designs). The final grouping includes the gusset designs and the "medium" and "large bow tie" designs. The designs to improve stress distribution had the lowest mean failure rates of all designs.

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