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Wireless sensor networks constitute the platform of a broad range of applications related to national security, surveillance, military, health care, and environmental monitoring. The coverage problem for Wireless Sensor Network (WSN) has been studied extensively in recent years, especially when combined with connectivity and energy efficiency. This paper focuses on the sensor replacement problem in wireless sensor networks consists of mobile sensors. Mobility equipped sensors are utilized to recover and maintain the overall coverage using the dynamic cluster concept. The proposed fault repair solution does not assume the localization information is available. Mobile sensor nodes make use of simple geometric operation to locate and replace dying nodes to recover or increase the existing coverage and connectivity.

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This paper presents an analytical method to measure the performance through memory of a proposed parallel processing computer architecture for image processing applications. We developed an analytical model of our proposed architecture and a conventional architecture with respect to the system's local and main memory to measure and compare the performances of these two systems. From our model we can evaluate the performance of the proposed architecture in terms of processor utilization, number of busy memory modules and the fraction of the programs data structure resident in local memory. The main idea behind our proposed architecture is to carry out image processing work in a highly parallel manner so that the response time is shorter. The proposed architecture keeps both the processor and the memory system as busy as possible in order to obtain faster response time and proper utilization of the hardware compared to a conventional parallel processing architecture. Our proposed architecture consists of an array of processing elements(PEs), a system control unit(SCU), interconnection network and memory modules. Each PE contains two central processing units(CPU), one is responsible for the execution of all non-memory operations and the other is responsible for all memory operations. The overall response time of a job is faster because we divide the actual execution and the memory operation into two separate entities and carry them out concurrently. We also present an image processing algorithm suitable for the proposed architecture and analyze their performance compared to the conventional system.