This paper presents a new approach for the definition and identification of a transistor model suitable for low-noise amplifier (LNA) design. The resulting model is very robust to layout modifications (i.e., source degeneration) providing accurate predictions of device noise-performance and small-signal parameters. Moreover, the described procedure is very robust since it does not require any numerical optimization, with possibly related problems like local minima and unphysical model parameters. The adopted model topology is based on a lumped element parasitic network and a black-box intrinsic device, which are both identified on the basis of full-wave lectromagnetic simulations, as well as noise and -parameter measurements. The procedure has been applied to three GaN HEMTs having different peripheries and a Ku-band LNA has been designed, demonstrating a very good agreement between measurements and predicted results

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Cascode field-effect transistors (FETs) are widely used in the design of monolithic microwave integrated circuits (MMICs), owing to their almost unilateral and broadband behavior. However, since a dedicated model of the cell is rarely provided by foundries, a suboptimal description built by replicating the standard foundry model for both the common source and common gate device is often adopted. This might limit the success of the MMIC design at the first foundry run. This paper describes an electromagnetic-based empirical model of cascode cells, covering topics from the formulation and identification procedures to the corresponding validation described in an exhaustive experimental section. A MMIC low-noise distributed amplifier case is then presented and the proposed model is used for circuit analysis and instability detection. Clear indication is provided about the improvement in the prediction of critical behaviors with respect to conventional modeling approaches. A cascode cell with a symmetric layout is also successfully modeled

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