Accurate EM-Based Modeling of Cascode FETs

Abstract

Cascode field-effect transistors (FETs) are widely used in the design of monolithic microwave integrated circuits (MMICs), owing to their almost unilateral and broadband behavior. However, since a dedicated model of the cell is rarely provided by foundries, a suboptimal description built by replicating the standard foundry model for both the common source and common gate device is often adopted. This might limit the success of the MMIC design at the first foundry run. This paper describes an electromagnetic-based empirical model of cascode cells, covering topics from the formulation and identification procedures to the corresponding validation described in an exhaustive experimental section. A MMIC low-noise distributed amplifier case is then presented and the proposed model is used for circuit analysis and instability detection. Clear indication is provided about the improvement in the prediction of critical behaviors with respect to conventional modeling approaches. A cascode cell with a symmetric layout is also successfully modeled

Direct extraction method for stripline packaged field effect transistor small signal equivalent circuit model

“…It can be found that L gx and L dx are very close and 2-3 times than L sx roughly. Figure 7 shows the extracted results for packaging capacitances C gx and C dx versus frequency at two different bias conditions (I ds 510 mA and 16 mA) by using (16) and (17). A remarkable flat frequency response can be observed.…”

“…Furthermore, although the direct extraction methods has been widely used for on-wafer FETs small signal model, however, these methods are not suitable for the determination of model parameters for packaged devices and have to be improved therefore [15,16]. Alternatively, a distributed parasitic network description based on electromagnetic (EM) simulation is adopted and used in conjunction with a conventional active device model [17]. The drawback is the geometric size of packaging is necessary to know in detail for EM simulation and time consuming.…”

LNA Design Based on an Extracted Single Gate Finger Model

“…The intrinsic portion of a standard two-finger test HEMT is extracted with a combination of an extended form of the EM extrinsic treatment in [3][4][5] for a single gate finger and the robust extraction technique of [6].…”

“…Ports 1 and 2 are the external measurement ports, while internal ports 3 to 4N+2 represent the differential gate-source and gate-drain ports of the intrinsic devices. In contrast to [3][4][5], the differential ports used here allow the impedance seen by all intrinsic device ports to vary according to the metal defining the manifold. This permits all the metal in the symmetric test device layout to be algebraically deembedded from measured s-parameters, immediately yielding the device parameters without any compaction, optimisation or iteration.…”

“…This effect was not a consideration for the lower f T process used in [4,5]. However, it is essential here particularly for accurate S 12 prediction at higher frequencies (Figs.…”