The convergence of computing and communications dictates building up rather than out. As consumers demand more functions in their hand-held devices, the need for more memory in a limited space is increasing, and integrating various functions into the same package is becoming more crucial. Over the past few years, die stacking has emerged as a powerful tool for satisfying these challenging Integrated Circuit (IC) packaging requirements.Previously, present authors reported on the thermal challenges of various die stacking architectures that included memory (volatile and non-volatile) only. In this paper, the focus is on stacking memory and the logic processor on the same substrate. In present technologies, logic processor and memory packages are located side-by-side on the board or they are packaged separately and then stacked on top of each other (Package-on-package [PoP]). Mixing memory and logic processor in the same stack has advantage and challenges, but requires the integration ability of economies-of-scale. Geometries needed were generated by using Pro/Engineer ® Wildfire ™ 2.0 as a Computer-Aided-Design (CAD) tool and were transferred to ANSYS ® Workbench ™ 10.0, where meshed analysis was conducted. Package architectures evaluated were rotated stack, staggered stack utilizing redistributed pads, and stacking with spacers, while all other parameters were held constant. The values of these parameters were determined to give a junction temperature of 100ºC, which is an unacceptable value due to wafer level electromigration. A discussion is presented in what parameters need to be adjusted in order to meet the required thermal design specification. In that light, a list of solutions consisting of increasing the heat transfer co-efficient on top of the package, the use of underfill, improved thermal conductivity of the PCB, and the use of a copper heat spreader were evaluated. Results were evaluated in the light of market segment requirements.