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We have developed a new method to simulate the effective rise time of current drawn by each cell in a microprocessor so that the total noise is consistent with values measured at the power and ground reference points inside the die. Normally, the measured values are much smaller than simulated values. In this paper, several exponential functions with varying time constants are staggered and combined at different starting time values to generate the effective current profile which was used for noise estimation. The model utilizes a realistic jitterbased distribution function compared to a step function used in existing models for the initial small amount of saturated current ramp. The practical model developed in this paper is useful for optimizing the cost and performance of microprocessors.Index Terms-Average power drawn by CMOS device, current ramp generation, microprocessor currrent simulation, noise simulation, power delivery, power delivery network (PDN), rise time of current, stastical process for power delivery.

In this paper we have shown a method by which we can determine the relationship between the time constant of the current ramp by the device and the corresponding ground and power noise of any silicon device, for a given Power Delivery network. This relationship can be used for statistical analysis of the power delivery network.