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In this work, Virtex-6 is Target 40nm FPGA Device. Xilinx ISE 14.1 is an ISE Design tool. RAM is a target design. Clock Gating is a technique which decreases clock power but increases Logic Power due to added Logic in Design. Irrespective of increase in number of Signal and IO buffer due to Clock Gating, there is significant decrease in IO Power and Dynamic Power due to decrease in number of frequency of device operating. The increase in Logic Power and Signal Power is relatively small in magnitude than decrease in clock power that translates to decrease in overall dynamic power. The clock power consumption of Clock Gated 65536x16-bit dual-port RAM is 38.89%(on 1GHz) and 41.3%(on 10GHz) lesser than the clock power consumption of 65536x16-bit dual-port RAM without using clock gating Techniques.

This paper is a study of detection of Brain tumor in MRI images by using simple Canny Edge Detection Technique , canny technique and Fuzzy c-means method by using Morphological Operations. The canny edge detection technique defines edges of the MRI image by using many parameter like thresholding, thinning etc. canny with morphological operation like dilation, erosion etc., where simply applied on it for getting better results, and fuzzy c-means method gives best results for segmentation of Brain tumor in MRI images. Segmentation is very important task for detection of area of intrest; after the segmentation morphological operation are applied to detect tumor in MRI brain images, these methods are tested over multiple MRI tumorous and nontumorous images.

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