Clock gated low power sequential circuit design

Dev, Mahendra Pratap; Baghel, Deepak; Pandey, Bishwajeet; Pattanaik, Manisha; Shukla, Anupam

doi:10.1109/cict.2013.6558136

Cited by 29 publications

(8 citation statements)

References 11 publications

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“…According to reference [1], More Power is consumed by Clock Enable and Less Power is consumed by Clock Gating technique. According to reference [2], Traditionally Power optimization is relegated to the synthesis and circuits level, now System Level and Register-Transfer-Level is used.…”

Section: Literature Reviewmentioning

confidence: 99%

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Clock Power Analysis of Low Power Clock Gated Arithmetic Logic Unit on Different FPGA

Gupta

2014

2014 International Conference on Computational Intelligence and Communication Networks

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This paper, deals with Latch Free Clock Gating technique for reduction of clock power and total power consumption in Low Power Arithmetic and Logic Unit and we have analysed power reduction on different FPGA devices. Without latch free clock gating technique in Low Power Arithmetic and Logic Unit the Contribution of Clock power was 39mW in Virtex-6 FPGA, 14mW in Virtex-5 FPGA, 24mW in Virtex-4 FPGA, 18mW in Spartan-3 FPGA, 18mW in Spartan-3E FPGA, 18mW in Spartan-6 FPGA, 5mW in Artix-7 FPGA of total power when device is operating at frequency of 1GHz. After implementation of latch free clock gating technique in Low Power Arithmetic and Logic Unit , Clock power contribution is 3mW in Virtex-6 FPGA, 5mW in Virtex-5 FPGA, 8mW in Virtex-4 FPGA, 5mW in Spartan-3 FPGA, 9mW in Spartan-3E FPGA, 7mW in Spartan-6 FPGA, 2mW in Artix-7 FPGA in total power. Total Power consumption is reduces to 1.41%, 1.33%, 2.53%, 7.65%, 2.88%, 3.38% and 2.64% on 40-nm Virtex-6 , 65-nm Virtex-5 , 90-nm Virtex-4, Spartan 3, Spartan 3E, Spartan-6 and Artix-7 target device respectively with device operating frequency is 1GHz. There is 92.31%, 64.29%, 66.67%, 72.22%, 50%, 61.11% and 60% reduction in clock power on 40-nm Virtex-6 , 65-nm Virtex-5 , 90-nm Virtex 4, Spartan 3, Spartan 3E, Spartan-6 and Artix-7 target device respectively with device operating frequency is 1GHz.

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Section: Literature Reviewmentioning

confidence: 99%

“…According to [1][2][3], clock power consumption has always a significant percent of total chip power. Hence, it is important to reduce clock power.…”

Section: Introductionmentioning

confidence: 99%

Clock Power Analysis of Low Power Clock Gated Arithmetic Logic Unit on Different FPGA

Gupta

2014

2014 International Conference on Computational Intelligence and Communication Networks

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“…By changing mapping style, we reduce number of LUT and D flip-flop used in implementation leads to area efficient design [6]. The main focus is study and analysis of various clock gating technique and design and analysis of clock gating based low power sequential circuit at RTL level [7].…”

Section: Related Workmentioning

confidence: 99%

Output load capacitance based low power implementation of UART on FPGA

Singh

Pandey

Kumar

et al. 2014

2014 International Conference on Computer Communication and Informatics

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Core dynamic power is independent of output load capacitance. IO power and static power is dependent on output load capacitance. In this work, we achieved 99.72% reduction in IOs power consumption of Universal Asynchronous Receiver Transmitter (UART) if we scale down output load from 10,000pf to 5pF in IOB setting of FPGA. Universal Asynchronous Receiver and Transmitter are a transceiver circuits that transmit/receive data between parallel and serial forms and vice versa. Design state of our design is high because no black box found. Bit width is high because 57.6% of primitives in RTL net list represent 1-bit logic. Here, IO power consumption is 17,226mW on 10,000pF output load which significantly reduce to 47mW on 5pF output load. Along with reduction in IOs power, we also observed 24.5% reduction in static power consumption from 1322mW on 10,000pF output load to 1004mW on 5pF output load. In our implementation on FPGA, we take Virtex-6 family, XC6VLX75T device, FF484 package, -1 speed grade, XST synthesis tool, ISim simulator, and Verilog as preferred HDL language.

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“…Our design is based on 28nm FPGA and 40nm FPGA and the code has been tested on Kintex-7 and Artix-7 FPGA. Clock gating technique is used to achieve energy efficiency in sequential circuit [3], 8-bit ALU [4] and 64-bit ALU [5], global reset ALU [6], and ITC'99-b01 Benchmark Circuit [7]. In [8], architecture of multiplier based on mathematics is discussed.…”

Section: Figure 1 Symbol Of Latin Unicode Readermentioning

confidence: 99%