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International audienceAn efficient multi-rate multi-stage architecture for the Comb decimation filter of Sigma-Delta ADCs is presented. Polyphase decomposition in all stages is used to reduce the operating frequency of the Comb filter. A systematic design procedure is developed in order to generate all possible combinations for the decimation factor of each stage. A third order Comb decimation filter with a total decimation factor of 16 is taken as a design example. The eight possible architectures are generated in two different CMOS processes. The performance of the generated architectures are compared in terms of power consumption, area and maximum operating frequency

Abstract-In this paper, we propose an automatic design procedure for the synthesis of a cascode LNA with inductive source degeneration. The proposed method is based on the precise characterization of noise figure, input impedance and gain. The design procedure is implemented in a C++ environment using a BSIM3v3-based tool for transistor sizing and a symbolic computation tool for circuit characterization. SystemC AMS can then be used to perform a system level simulation of a complete RF receiver using precise model of the LNA. Considering the complete equivalent model for the transistors and the inductors, two LNAs operating at 2.4 GHz and 935 MHz are synthesized and characterized for a 130 nm CMOS process. The generated accurate model is then used in a high-level simulation of a complete QPSK-based RF receiver to study the effect of the LNA noise figure on the Bit Error Rate of the receiver.