No abstract

International audienceAn efficient multi-rate multi-stage architecture for the Comb decimation filter of Sigma-Delta ADCs is presented. Polyphase decomposition in all stages is used to reduce the operating frequency of the Comb filter. A systematic design procedure is developed in order to generate all possible combinations for the decimation factor of each stage. A third order Comb decimation filter with a total decimation factor of 16 is taken as a design example. The eight possible architectures are generated in two different CMOS processes. The performance of the generated architectures are compared in terms of power consumption, area and maximum operating frequency

This work presents a new automatic mechanism to explore the solution space between Field Programmable Gate Arrays (FPGAs) and Application-Specific Integrated Circuits (ASICs). This new solution is termed as an Application-Specific Inflexible FPGA (ASIF) [Parvez et al. 2009]. An ASIF can be considered as an FPGA with reduced flexibility, or as a reconfigurable ASIC that can implement a set of application circuits which will operate at mutually exclusive times. Execution of different application circuits can be switched by loading their respective bitstream on an ASIF. An ASIF that is reduced from a heterogeneous FPGA is termed as a heterogeneous ASIF. It is shown that a standard-cell-based heterogeneous ASIF for a set of 10 opencore application circuits is 9.6 times smaller than a single-driver mesh-based heterogeneous FPGA. The area gap between ASIC and ASIF is not too significant; however, it can be reduced by designing repeatedly used components of ASIF in full-custom. Unlike an ASIC, an ASIF is a reprogrammable device that can be used to reprogram new or modified circuits at a limited scale.

Proliferation of mutually exclusive applications on circuits and the higher cost of silicon make the resource sharing more and more important. The state-of-the-art synthesis tools may often be unsatisfactory. Their efficiency may depend on the hardware description style. Nevertheless, today, different applications in a circuit can be developed by different developers. This paper proposes an efficient method to improve resource sharing between mutually exclusive applications with no dependence on the coding style. It takes the advantage of the possibility of resource sharing as done in FPGA and of predefined multiple functions as in ASIC.

Multiple Context ASIC (mASIC) is a circuit grouping a set of designs (applications) which operates at mutually exclusive times. In this paper we propose to take this particularity into account when we run logic synthesis. The idea is to maximize logic resources sharing between designs to reduce the total resulting area. Once used on mASIC for a set of 5 benchmark designs, our synthesizing technique reduces area by 28% compared to the sum of the 5 individual ASIC areas.