A Top-Down Optimization Methodology for Mutually Exclusive Applications

Many digital systems provide multiple but closely related functionalities, not all of them are required simultaneously. Dedicated hardware solution for each functionality will waste too much silicon area. This work presents automatic generation of a shared hardware solution for a set of functionalities which will execute only one functionality at a time. This shared hardware solution is termed as “Multi-Circuit”. A Multi-Circuit can be embedded as a configurable component in a System-on-Chip (SoC) design. Multi-Circuit is generated by initially mapping a given set of application functionalities on a common reconfigurable platform. Later on, all the unused logic and routing resources are efficiently removed from the reconfigurable hardware. Experiments reveal that Multi-Circuit is 18–42% smaller than the previously proposed technique named Application Specific Inflexible FPGA (ASIF). Multi-Circuit is 73–84% smaller than its corresponding FPGA design.

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“Multi-Circuit”: Automatic Generation of an Application Specific Configurable Core for Known Set of Application Circuits

Iqbal

Parvez

Rashid

2016

J CIRCUIT SYST COMP

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An Application Specific Reconfigurable Architecture with Reduced Area and Static Memory Cells

Iqbal

Parvez

Hussain³

et al. 2020

J CIRCUIT SYST COMP

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An Application Specific Inflexible FPGA (ASIF) is a tailored design, for a given group of known circuits, which is generated by extensively reducing the routing resources of an FPGA. In an ASIF, different dynamically reconfigurable application circuits are initially mapped and tested on an FPGA fabric. Subsequently, the FPGA fabric is reduced to achieve an efficient architecture for known application circuits. However, a large portion of ASIF is still occupied by fully flexible logic blocks, containing the same amount of area and SRAM memory cells, as found in a traditional FPGA. Thus, here lies a potential to further optimize the logic blocks of an ASIF at the expense of removing or reducing their reconfigurability. This work optimizes the logic blocks of an ASIF through the SRAM-Table sharing technique, without compromising their reconfigurability. Moreover, the routing channels of ASIF are further optimized by applying the Boolean functions (Gates) insertion technique. The applied techniques (SRAM-Table sharing and Boolean functions insertion) not only reduce the area, delay and power, but also minimize the reconfiguration time, bitstream size and the size of external memory required to store the bitstream of circuits. This optimized version of ASIF is termed as ASIF[Formula: see text]. Furthermore, an embedded FPGA in a System-on-Chip that requires the partial dynamic reconfiguration for known circuits, can be automatically reduced to an ASIF[Formula: see text]. It is found through experimental results that an ASIF[Formula: see text] is 4–9[Formula: see text] area-efficient and requires [Formula: see text] lesser number of SRAM cells, as compared to the previously proposed ASIF for a group of 2–5 circuits. It also achieves 34–53[Formula: see text] area saving as compared to a traditional FPGA.

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Genetic-Algorithm-Based FPGA Architectural Exploration Using Analytical Models

Mehri

Alizadeh

2016

ACM Trans. Des. Autom. Electron. Syst.

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FPGA architectural optimization has emerged as one of the most important digital design challenges. In recent years, experimental methods have been replaced by analytical ones to find the optimized architecture. Time is the main reason for this replacement. Conventional Geometric Programming (GP) is a routine framework to solve analytical models, including area, delay, and power models. In this article, we discuss the application of the Genetic Algorithm (GA) to the design of FPGA architectures. The performance model has been integrated into the Genetic Algorithm framework in order to investigate the impact of various architectural parameters on the performance efficiency of FPGAs. This way, we are able to rapidly analyze FPGA architectures and select the best one. The main advantages of using GA versus GP are concurrency and speed. The results show that concurrent optimization of high-level architecture parameters, including lookup table size ( K ) and cluster size ( N ), and low-level parameters, like scaling of transistors, is possible for GA, whereas GP does not capture K and N under its concurrency and it needs to exhaustively search all possible combinations of K and N . The results also show that more than two orders of magnitude in runtime improvement in comparison with GP-based analysis is achieved.

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A Top-Down Optimization Methodology for Mutually Exclusive Applications

Cited by 3 publications

References 14 publications

“Multi-Circuit”: Automatic Generation of an Application Specific Configurable Core for Known Set of Application Circuits

“Multi-Circuit”: Automatic Generation of an Application Specific Configurable Core for Known Set of Application Circuits

An Application Specific Reconfigurable Architecture with Reduced Area and Static Memory Cells

Genetic-Algorithm-Based FPGA Architectural Exploration Using Analytical Models

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