The problem of on-line testing of asynchronous circuits is analysed, several infrastructures are proposed and a selfchecking tree checker is designed. The checker uses ondemand self-test, which reduces power consumption and guarantees bounded self-test period. Objects under test are tested by observing protocols at their primary inputs and outputs. The checker does not slow down the functional system, as it only samples the signals. The protocols are checked by identifying enabled and refused signal transitions in each state of the system. The fault coverage of internal faults of the checker is calculated. Simulation results are included.

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Abstract-Neuromorphic chips are used to model biologically inspired Spiking-Neural-Networks(SNNs) where most models are based on differential equations. Equations for most SNN algorithms usually contain variables with one or more e x components. SpiNNaker is a digital neuromorphic chip that has so far been using pre-calculated look-up tables for exponential function. However this approach is limited because the memory requirements grow as more complex neural models are developed. To save already limited memory resources in the next generation SpiNNaker chip, we are including a fast exponential function in the silicon. In this paper we analyse iterative algorithms for elementary functions and show how to build a single hardware accelerator for exp and natural log, for a neuromorphic chip prototype, to be manufactured in a 22 nm FDSOI process. We present the accelerator that has algorithmic level approximation control, allowing it to trade precision for latency and energy efficiency. As an addition to neuromorphic chip application, we provide analysis of a parameterized elementary function unit that can be tailored for other systems with different power, area, accuracy and latency constraints.

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