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This paper proposes a one-transistor dynamic random-access memory (1 T DRAM) with local partial insulator (LPI) to increase data retention time. Proposed 1 T DRAM cell has improved retention characteristics because LPIs inhibit stored carrier movement with a high energy barrier. Definition of retention time in the proposed 1 T DRAM is introduced at hold “0” state. Device optimization with parameter variation is investigated with device simulation. As the barrier length increases, retention characteristics can be improved but it also causes a decrease in the I1/I0 current ratio. An increase in LPI length can improve the retention characteristics but reduce the I1/I0 current ratio. It was confirmed that the retention characteristics were improved as the hold bias was decreased. Finally, the retention characteristics were optimized when the LPI was precisely formed at the junction boundary.