The hybrid fiber coax architecture deployed by the cable service providers has been successful in capturing a substantial piece of the residential broadband access market. In the United States over five million homes connect to the Internet using DOCSIS 1 cable modems. In this article we describe an evolution path to enhance the HFC plant to provide, initially, Gigabit Ethernet (and eventually multi-Gigabit Ethernet) on the trunk and feeder portions, and 100 Mb/s Ethernet on the subscriber drops. This next-generation HFC network will enable cable service providers to address the vast and underserved small and medium-sized business market, as well as offer emerging applications and services to the residential market. THE HFC INFRASTRUCTURE AND DOCSISThe cable plant, whose original objective was to deliver analog TV signals to homes obstructed from line-of-sight reception, is typically organized in a trunk and branch topology. Over time, however, cable service offerings have grown, adding numerous commercial and paid programming services, telephony, and asymmetrical data

Vector matrix multiplication computation underlies major applications in machine vision, deep learning, and scientific simulation. These applications require high computational speed and are run on platforms that are size, weight, and power constrained. With the transistor scaling coming to an end, existing digital hardware architectures will not be able to meet this increasing demand. Analog computation with its rich set of primitives and inherent parallel architecture can be faster, more efficient, and compact for some of these applications. One such primitive is a memristor-CMOS crossbar array-based vector matrix multiplication. In this article, we develop a memristor-CMOS analog coprocessor architecture that can handle floating-point computation. To demonstrate the working of the analog coprocessor at a system level, we use a new electronic design automation tool called PSpice Systems Option, which performs integrated cosimulation of MATLAB/Simulink and PSpice. It is shown that the analog coprocessor has a superior performance when compared to other processors, and a speedup of up to 12 × when compared to projected GPU performance is observed. Using the new PSpice Systems Option tool, various application simulations for image processing and solutions to partial differential equations are performed on the analog coprocessor model.<?enlrg 3pt?>

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