We demonstrate for the first time full-scale integration of top-pinned perpendicular MTJ on 300 mm wafer using CMOS-compatible processes for spin-orbit torque (SOT)-MRAM architectures. We show that 62 nm devices with a Wbased SOT underlayer have very large endurance (> 5x10 10 ), sub-ns switching time of 210 ps, and operate with power as low as 300 pJ.Introduction: The introduction of non-volatility (NV) at the cache level in advance logic nodes is sought as it would lead to a large decrease of the power consumption of microprocessors. Among NV memory technologies, spin-transfer torque (STT) MRAM has gained a lot of attention due to its scalability, low power and high speed, as well as compatibility with scaled CMOS processes and voltages. Despite all these advantages, STT-MRAM cannot operate reliably at ns and sub-ns scales due to large incubation delays [1,2], making it an unsuitable solution to tackle L1/2 SRAM cache replacement. In addition, the shared read/write path can impair the read reliability, while the write current can impose severe stress on the MTJ, leading to time dependent degradation of the memory cell. To mitigate these issues, spin-orbit torque (SOT)-MRAM has been recently proposed [2,3]. SOT induces switching of the free layer (FL) of the MTJ by injecting an in-plane current in an adjacent SOT layer, typically with the assistance of a static in-plane magnetic field [2]. This enables a three terminal MTJ-based concept that isolates the read/write path (Fig. 1), significantly improving the device endurance and read stability. Moreover, due to SOT spin transfer geometry, incubation time is negligible which allows for reliable switching operation at sub-ns timescales [4,5]. Here, we report the first successful integration of SOT-MTJ cells on 300 mm wafers using CMOS-compatible processes. We demonstrate low power sub-ns switching and pathways for further optimization. Finally, excellent endurance and absence of electro-migration effect of ultrathin SOT layers are shown.Integration flow: We used a SOT dedicated mask set in the imec 300 mm fab. The main steps of the integration process are summarized in Fig. 2: a SOT-MTJ stack is deposited on smooth bottom electrodes (BE), which are fabricated using a tungsten (W) damascene process. The MTJ is top pinned and consist of SOT/CoFeB/MgO/CoFeB/SAF perpendicularly magnetized (PMA) stack, where the SOT layer is W-based. Specific stop etch conditions have been developed to leave the SOT layer intact while patterning the MTJ pillar without producing sidewall shorts across the MgO barrier (Fig. 2c,d). Subsequently, the SOT layer is etched to form the three terminal device and a dual damascene Cu top electrode (TE) was fabricated to complete the electrical connection ( Fig. 2a).Stack development: SOTs possess a damping-like term (τDL) attributed to spin Hall and a field-like term (τFL) attributed to interface interactions [2]. Recent work indicates that τDL triggers switching while τFL accelerates it [5]. Charge-to-spin conversion efficiency parameters θDL and...

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