The monolithic hetero-integration of III/V materials on Si substrates could enable a multitude of new device applications and functionalities which would benefit from both the excellent optoelectronic properties of III/V compound materials and the well-established and highly mature Si manufacturing technologies. Due to the lattice mismatch between most III/V compound semiconductors and Si substrates, monolithic growth inevitably leads to the formation of strain releasing defects which degrade the final device performance and reliability. This review paper provides an overview of current approaches and methods to control the defect formation in monolithic III/V hetero-epitaxy on (001) Si substrates. The focus is on understanding the mechanisms of defect nucleation, manipulation and confinement in order to eventually realize active III/V device layers on Si substrates with high crystalline quality. For details about device applications numerous references are listed. Although many different integration approaches are discussed in the literature, there are two main concepts for the hetero-epitaxial growth of III/V material on Si: growth on blanket Si wafers and selective area growth on patterned Si substrates. Both methods have their advantages and disadvantages with respect to defect control and could potentially enable the integration of different III/V devices on a Si platform.

This study relates to the heteroepitaxy of InP on patterned Si substrates using the defect trapping technique. We carefully investigated the growth mechanism in shallow trench isolation trenches to optimize the nucleation layer. By comparing different recess engineering options: rounded-Ge versus V-grooved, we could show a strong enhancement of the crystalline quality and growth uniformity of the InP semiconductor. The demonstration of III-V heteroepitaxy at scaled dimensions opens the possibility for new applications integrated on Silicon.

In this work, we demonstrate the selective area growth of high quality InP layers in submicron trenches on exactly (001) oriented Si substrates by using a thin Ge buffer layer. Antiphase domain boundaries were avoided by annealing at the Ge surface roughening temperature to create additional atomic steps on the Ge buffer layer. The mechanism of Ge surface atomic step formation and the corresponding step density control method are illustrated. The elimination of antiphase boundaries from the optimized Ge buffer layer, together with the defect necking effect, yield defect-free top InP layers inside the trenches.

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We present a comprehensive study of Positive Bias Temperature Instability (PBTI) in In 0.53 Ga 0.47 As devices with Al 2 O 3 gate oxide, and with varying thickness of the channel quantum well. We show significant instability of the device electrical parameters induced by electron trapping into a wide distribution of defects in the high-k layer, with energy levels just above the InGaAs conduction band. A significant PBTI dependence on the channel thickness is found and ascribed to quantization effects. We argue that, in order to be relevant for production, the superior transport properties of III-V channels will need to be demonstrated with more stable high-k gate stacks.