2014
DOI: 10.1063/1.4862044
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Heteroepitaxy of InP on Si(001) by selective-area metal organic vapor-phase epitaxy in sub-50 nm width trenches: The role of the nucleation layer and the recess engineering

Abstract: This study relates to the heteroepitaxy of InP on patterned Si substrates using the defect trapping technique. We carefully investigated the growth mechanism in shallow trench isolation trenches to optimize the nucleation layer. By comparing different recess engineering options: rounded-Ge versus V-grooved, we could show a strong enhancement of the crystalline quality and growth uniformity of the InP semiconductor. The demonstration of III-V heteroepitaxy at scaled dimensions opens the possibility for new appl… Show more

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Cited by 94 publications
(74 citation statements)
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“…Low defect density growth of GaAs 23 , InP 24,25 and InGaAs 26 compounds using selective area growth on prepatterned (001)-silicon was achieved, leading to the demonstration of the world's first III-V FinFET devices grown on a 300 mm substrate. Here we leverage this process to demonstrate room temperature laser operation of wafer scale integrated InP lasers directly grown on standard (001)-silicon substrates.…”
mentioning
confidence: 99%
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“…Low defect density growth of GaAs 23 , InP 24,25 and InGaAs 26 compounds using selective area growth on prepatterned (001)-silicon was achieved, leading to the demonstration of the world's first III-V FinFET devices grown on a 300 mm substrate. Here we leverage this process to demonstrate room temperature laser operation of wafer scale integrated InP lasers directly grown on standard (001)-silicon substrates.…”
mentioning
confidence: 99%
“…Except for the first 20nm thick dark layer at the InP-Si interface and some stacking faults along the trench originating from the complex growth process, hardly any dislocations can be found in the material. The bottom defective layer is formed during the early stage of the epitaxy process 25 . The well-controlled low temperature nucleation process accommodates the entire lattice mismatch within a few tens of nanometers, allowing for fully relaxed and threading dislocation-free InP growth in the next step.…”
mentioning
confidence: 99%
“…Significant progress has been reported over the last 4-5 years for the integration of Ge channels on Si for enhanced pMOS devices [4][5][6]. However, similar progress for III-V materials has proved to be far more difficult, and only recently has an important breakthrough been reported for integrating device quality III-V materials on 300 mm Si wafers [7,8]. The lattice mismatch with respect to Si (4% for Ge, 8% for InP, 12% for InAs) is an important source similar mechanism for InP dissolution in aqueous HCl solutions based on undissociated HCl [25].…”
Section: Introductionmentioning
confidence: 99%
“…21 , 23 , 24 Figure 5 illustrates InP grown selectively on a 300-mm-diameter Si in nanoscale trenches. 24 These techniques are being advanced in facilities combining growth and nanofabrication capabilities to create metamorphic materials in a deterministic fashion. …”
Section: Guest Editorsmentioning
confidence: 99%