Chemical transformations in paintings often induce discolorations, disturbing the appearance of the image. For an appropriate conservation of such valuable and irreplaceable heritage objects, it is important to have a good know-how on the degradation processes of the (historical) materials: which pigments have been discolored, what are the responsible processes, and which (environmental) conditions have the highest impact on the pigment degradation and should be mitigated. Pigment degradation is already widely studied, either by analyzing historical samples or by accelerated weathering experiments on dummies. However, in historic samples several processes may have taken place, increasing the complexity of the current state, while aging experiments are time-consuming due to the often extended aging period. An alternative method is proposed for a fast monitoring of degradation processes of semiconductor pigments, using an electrochemical setup mimicking the real environment and allowing the identification of harmful environmental parameters for each pigment. Examples are given for the pigments cadmium yellow (CdS) and vermilion (α-HgS).

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This work reports on some key integration aspects for 3D devices fabrication, focusing first on the impact of thermal and plasma treatments at gate module for triple-gate finFETs and their ultimate scaling limit: gate-all-around (GAA) nanowire (NW) FETs, which can be implemented in a lateral (with one or more lateral wires vertically stacked) or vertical configuration. The selected doping schemes and gate metals can also be powerful knobs to engineer the interface properties. In addition, specific steps for lateral NWFETs, such as the wires release process, will be addressed here. Vertical NWFETs, corresponding to the move from a 2D to a 3D CMOS layout, have the potential for lower parasitics, reduced power consumption and for enabling smaller, higher performing SRAM bitcells. We will present here alternative, novel approaches for building and characterizing these devices, focusing on channelfirst schemes with improved process control, while tackling critical etch-layout dependences.