Scalability of InGaAs gate-all-around FET integrated on 300mm Si platform: Demonstration of channel width down to 7nm and L&lt;inf&gt;g&lt;/inf&gt; down to 36nm

Zhou, Xiaoxin; Waldron, Niamh; Boccardi, G.; Sebaai, Farid; Merckling, Clément; Eneman, G.; Sioncke, Sonja; Nyns, L.; Opdebeeck, A.; Maes, Jan Willem; Xie, Qingyun; Givens, M. E.; Tang, Fu; Jiang, Xiaoqiang; Guo, Wei; Kunert, Bernardette; Teugels, Lieve; Devriendt, K.; Hernandez, Arturo Sibaja; Franco, J.; Dorp, Dennis van; Barla, K.; Collaert, N.; Thean, A.

doi:10.1109/vlsit.2016.7573420

Cited by 13 publications

(11 citation statements)

References 2 publications

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“…Considerable progress has also been made recently in InGaAs based MOSFETs demonstrating high performance at low supply voltages, both on InP substrate, 8,9) and on silicon platform. [10][11][12] Besides the recent consideration as n-channel material for CMOS technology, InGaAs based material system has traditionally been utilized as channel in highelectron mobility transistors (HEMTs) for high-frequency applications. Benefiting from the developments made in InGaAs based FETs, impressive cut-off frequencies have been demonstrated in MOS-HEMT and MOSFET architectures.…”

Section: Introductionmentioning

confidence: 99%

Three-dimensional monolithic integration of III–V and Si(Ge) FETs for hybrid CMOS and beyond

Deshpande

Djara

O’Connor

et al. 2017

Jpn. J. Appl. Phys.

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Three-dimensional (3D) monolithic integration can enable higher density and has the potential to stack independently optimized layers at transistor level. Owing to high mobility and lower processing temperatures, InGaAs is well-suited to be used as the top layer channel material in 3D monolithic integration along with Si/Si(Ge) FETs. A review of recent progress to develop InGaAs-on-Si(Ge) 3D Monolithic technology is presented here.

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Section: Introductionmentioning

confidence: 99%

Three-dimensional monolithic integration of III–V and Si(Ge) FETs for hybrid CMOS and beyond

Deshpande

Djara

O’Connor

et al. 2017

Jpn. J. Appl. Phys.

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“…Whatever, the next step in CMOS technology is, we have to implement the right process for integration of III-V materials on silicon, which are categorized in the three following ways: blanket epitaxy [184,185], selective epitaxy [186,187], and wafer bonding [188].…”

Section: Channel Materials For Beyond Moore Eramentioning

confidence: 99%

“…IMEC demonstrated III-V FinFET and III-V parallel Gate-All-Around (GAA) FET on a silicon substrate by ART technology [186]. They reported InGaAs GAA FETs with channel width down to 7 nm and L g down to 36 nm, which is the smallest dimensions reported about III-V materials devices on 300 mm Si wafer.…”

Section: Channel Materials For Beyond Moore Eramentioning

confidence: 99%

“…( b ) 9.5 nm-wide channel obtained from 2 cycles of WHALE* where 1 nm conformal interfacial layer was grown by ALD before HfO 2 deposition. ( c ) 7 nm-wide channel obtained from 5 cycles of WHALE* with the same gate stack as shown in ( b ) are used, and ( d ) along the trench showing L g of 36 nm [186]. * WHALE stands for Wet HCl-based Atomic Layer Etch.…”

Section: Figurementioning

confidence: 99%

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Miniaturization of CMOS

Radamson

Zhang

et al. 2019

Micromachines

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When the international technology roadmap of semiconductors (ITRS) started almost five decades ago, the metal oxide effect transistor (MOSFET) as units in integrated circuits (IC) continuously miniaturized. The transistor structure has radically changed from its original planar 2D architecture to today’s 3D Fin field-effect transistors (FinFETs) along with new designs for gate and source/drain regions and applying strain engineering. This article presents how the MOSFET structure and process have been changed (or modified) to follow the More Moore strategy. A focus has been on methodologies, challenges, and difficulties when ITRS approaches the end. The discussions extend to new channel materials beyond the Moore era.

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“…Alternatively, sophisticated integration approaches like selective area growth (SAG) in highly confined patterns, epitaxial lateral overgrowth 6 , deposition on V-groove-patterned substrates 7,8 , III-V nanowire growth 9 or quantum-well-in-nanopillar growth 10 are used to confine the defect formation. Especially aspect ratio trapping (ART) 11,12 a) Electronic mail: Dries.VanThourhout@UGent.be b) Electronic mail: Bernardette.Kunert@imec.be c) also at IMEC, Kapeldreef 75, 3001 Heverlee, Belgium in trenches was successfully applied to realize first III-V transistors on 300 mm Si substrates 13,14 but also explored for laser applications 15,16 . The heteroepitaxial growth in very narrow trenches is very beneficial to reduce the TD density but restricts the total volume of III-V material.…”

Section: Introductionmentioning

confidence: 99%

Time-resolved photoluminescence characterization of InGaAs/GaAs nano-ridges monolithically grown on 300 mm Si substrates

Shi

Kreuzer

Gerhardt

et al. 2020

Journal of Applied Physics

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The monolithic growth of III-V materials directly on Si substrates provides a promising integration approach for passive and active silicon photonic integrated circuits (PICs) but still faces great challenges in crystal quality due to misfit defect formation. Nano-ridge engineering (NRE) is a new approach which enables the integration of III-V based devices on trench-patterned Si substrates with very high crystal quality. Using selective area growth (SAG) III-V material is deposited into narrow trenches to reduce the dislocation defect density by aspect ratio trapping (ART). The growth is continued out of the trench pattern and a box-shaped III-V nano-ridge is engineered by adjusting the growth parameters. A flat (001) GaAs nano-ridge surface enables the epitaxial integration of a common InGaAs/GaAs multi-quantum-well (MQW) structure as an optical gain medium to build a laser diode. In this study a clear correlation is found between the photoluminescence (PL) lifetime, extracted from time-resolved photoluminescence (TRPL) measurements, with the InGaAs/GaAs nano-ridge size and defect density, which are both predefined by the nano-ridge related pattern trench width. Through addition of an InGaP passivation layer, a MQW PL lifetime of up to 800 ps and 1000 ps is measured, when pumped at 900 nm (QWs only excited) and 800 nm (QWs + barrier excited) respectively. Addition of a bottom carrier blocking layer further increases this lifetime to ∼ 2.5 ns (pumped at 800 nm), which clearly demonstrates the high crystal quality of the nano-ridge material. These TRPL measurements not only deliver a quick and valuable feedback about the III-V material quality but also provide an important understanding for the heterostructure design and carrier confinement of the nano-ridge laser diode.

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Scalability of InGaAs gate-all-around FET integrated on 300mm Si platform: Demonstration of channel width down to 7nm and L<inf>g</inf> down to 36nm

Cited by 13 publications

References 2 publications

Three-dimensional monolithic integration of III–V and Si(Ge) FETs for hybrid CMOS and beyond

Three-dimensional monolithic integration of III–V and Si(Ge) FETs for hybrid CMOS and beyond

Miniaturization of CMOS

Time-resolved photoluminescence characterization of InGaAs/GaAs nano-ridges monolithically grown on 300 mm Si substrates

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