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This paper presents two novel algorithms for the calculation of semiconductor losses of a three‑phase quasi-Z-source inverter (qZSI). The conduction and switching losses are calculated based on the output current‑voltage characteristics and switching characteristics, respectively, which are provided by the semiconductor device manufacturer. The considered inverter has been operated in a stand‑alone operation mode, whereby the sinusoidal pulse width modulation (SPWM) with injected 3rd harmonic has been implemented. The proposed algorithms calculate the losses of the insulated gate bipolar transistors (IGBTs) and the free-wheeling diodes in the inverter bridge, as well as the losses of the impedance network diode. The first considered algorithm requires the mean value of the inverter input voltage, the mean value of the impedance network inductor current, the peak value of the phase current, the modulation index, the duty cycle, and the phase angle between the fundamental output phase current and voltage. Its implementation is feasible only for the Z-source-related topologies with the SPWM. The second considered algorithm requires the instantaneous values of the inverter input voltage, the impedance network diode current, the impedance network inductor current, the phase current, and the duty cycle. However, it does not impose any limitations regarding the inverter topology or switching modulation strategy. The semiconductor losses calculated by the proposed algorithms were compared with the experimentally determined losses. Based on the comparison, the correction factor for the IGBT switching energies was determined so the errors of both the algorithms were reduced to less than 12%.

A quasi-Z-source inverter (qZSI) is a single-stage inverter that enables a boost of the input dc voltage through the utilization of a so-called shoot-through state (STS). Generally, the efficiency of the qZSI depends on the utilized STS injection method to a significant extent. This paper presents a novel method of STS injection, called the zero-sync method, in which the STS occurrence is synchronized with the beginning of the zero switching states (ZSSs) of the three-phase sinusoidal pulse width modulation (SPWM). In this way, compared to the conventional STS injection method, the total number of switchings per transistor is reduced. The ZSSs are detected by utilizing the SPWM pulses and the logic OR gates. The desired duration of the STS is implemented by utilizing the LM555CN timer. The laboratory setup of the three-phase qZSI in the stand-alone operation mode was built to compare the proposed zero-sync method with the conventional STS injection method. The comparison was carried out for different values of the switching frequency, input voltage, duty ratio, and load power. As a result of the implementation of the zero-sync method, the qZSI efficiency was increased by up to 4%. In addition, the unintended STSs, caused by the non-ideal switching dynamics of the involved transistors, were successfully eliminated by introducing the optimal dead-time as part of the modified zero-sync method. As a result, the efficiency was increased by up to 12% with regard to the conventional method.

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