With the advancement of beyond-CMOS devices to keep Moore’s law alive, several emerging devices have found application in a wide range of applications. Spintronic devices offer low power, non-volatility, inherent spatial and temporal randomness, simplicity of integration with a silicon substrate, etc. This makes them a potential candidate for next-generation hardware options. This work explores the giant spin Hall effect (GSHE)-driven spin-orbit torque (SOT) magnetic tunnel junction (MTJ) as a potential candidate for creating an externally triggered hardware Trojan and insertion into logic-locked hardware security considering the effect of process and temperature variations.

The increasing threat of security attacks on hardware security applications has driven research towards exploring beyond CMOS devices as an alternative. Spintronic devices offer advantages like low power, non-volatility, inherent spatial and temporal randomness, simplicity of integration with a silicon substrate, etc., making them a potential candidate for next-generation hardware security systems. In this work, we explore the Giant Spin Hall effect (GSHE) driven spin-orbit torque magnetic tunnel junction (MTJ) implementing physically unclonable function (PUFs). The effect of process variation is considered in key MTJ parameters like TMR ratio, free and oxide layer thickness following Gaussian distribution, and Monte-Carlo simulations to determine the effect of the process variations. A unique challenge-response (C-R) pair is obtained utilizing the inherent variations in magnetization dynamics of the free layer due to process variations.INDEX TERMS Giant spin Hall Effect (GSHE), hardware security, magnetic tunnel junction (MTJ), physical unclonable functions (PUFs), spintronic, spin-orbit torque (SOT).

With the advancement of beyond CMOS devices, a new approach to utilize the inherent physics of such emerging structures for various applications is of great interest in recent research. Spintronics-based devices offer key advantages like ease of fabrication with Si-substrate, non-volatile memory, low operational voltage, and non-linear device characteristics, which have shown potential for several emerging fields of study. Hardware security is one of the key interest areas which heavily relies on CMOS-based ICs, and the defense and attack mechanism is mostly based on CMOS-based structures. This work explores several emerging structures based on 2T/3T magnetic tunnel junctions (MTJ) for possible logic locking applications in hardware security systems. We demonstrate the effect of MTJ-based devices to implement logic locking even in the presence of process variations, and its ability of robustness to device imperfections has been evaluated using monte carlo simulations for practical applications.INDEX TERMS CMOS technology, hardware security, logic locking, magnetic tunnel junction (MTJ), spintronics, spin-orbit torque (SOT), spin-transfer torque (STT), voltage-controlled magnetic anisotropy (VCMA).

Emerging spintronics devices in recent research have received much interest in various fields. Their unique physical aspects are being explored to keep Moore’s law alive. Therefore, the hardware security aspects of system-on-a-chip (SoC) designs using spintronics devices becomes important. Magnetic tunnel junctions (MTJ) are a potential candidate in spintronics-based devices for beyond-CMOS applications. This work uses voltage-gated spin-orbit torque-assisted magnetic tunnel junction (VGSOT-MTJ) based on the Verilog-A behavioral model to design a possible logic-locking system for hardware security. Compared with the SOT MTJ, which uses a heavy metal strip below the MTJ stack, VGSOT-MTJ has an antiferromagnetic (AFM) strip that utilizes the voltage-controlled magnetic anisotropy (VCMA) effect to significantly reduce the JSOT,critical. To design the logic-locking block, we performed a Monte Carlo analysis to account for the effect of process variation (PV) on critical MTJ parameters. Eye diagram tests and mask designing were performed, which included the effect of thermal noise and PV for high-speed digital circuit operations. Finally, transient performance was analyzed to demonstrate the VGSOT-MTJ’s ability to design logic-locking blocks from the circuit operation perspective.

The globalization of the Integrated Circuits supply chain has increased threats from untrusted entities involved in the process. Several mechanisms, such as logic locking, watermarking and split manufacturing, are widely used to ensure hardware security. This study describes a novel method for creating hardware watermarks inspired by finite-state machines. It makes use of the unique physical property of magnetic tunnel junctions that are based on spin-orbit torque. The design strategy is described in detail, including the use of an EDA tool to analyze and take advantage of the unique switching properties of MTJ, their non-volatility, and their reliance on an external magnetic field to direct information through a predetermined order of states in a manner akin to an FSM. Furthermore, the performance prospects are analyzed using Monte Carlo simulations. For the 5% and 10% of process variation in the key MTJ parameters, the accuracy of 100% and 99.80%, respectively, are achieved. In control signal voltage variation, a tolerance of 9% (0.91V) is observed. The required state transition is not altered, demonstrating a tolerable sensitivity to temperature variation from 250K to 350K. The security aspects and methodology for the approach are explained to ensure a more robust and practical application, and finally, a comparison is made with other FSM-based watermarks.INDEX TERMS Hardware watermarks, hardware security, spintronics, spin-orbit torque (SOT), magnetic tunnel junction (MTJ), finite-state machine (FSM).