In this paper, the complementary and selective characteristics of ECL (Emitter-Coupled Logic) circuit are fully taken advantage to implement various logic gates including MUX, XOR, AND, NAND, OR, and so on. From the analysis, we find that one ECL circuit can realize many relative logic functions, which is more flexible than CMOS logic. We conclude that if the characteristics of ECL circuit are fully taken advantages, the design of logic functions can be very easy.

This paper presents the design of a 10 bit 2GHz digital to analog converter circuit. The digital to analog converter circuit adopts the design simulation of HBT process, able to work at a sampling frequency of 2 GHz, the highest sampling frequency can reach about 4 GHz. The SFDR of the digital to analog converter circuit can reach 62dB (simulation work at 2 GHz), the SFDR can reach 45 dB (simulation work at 4 GHz). Early product parameters of the digital to analog converter circuit (working in 1 GHz sampling frequency) are as follows: the narrowband SFDR parameter can be achieved 81 dB, broadband SFDR parameters can reach 46 dB.

High speed encoder is the key element of high speed analog-to-digital converter (ADC). Therefor the type of encoder, the type of code, bubble error suppression and bit synchronization must be taken into careful consideration especially for folding and interpolating ADC. To reduce the bubble error which may resulted from the circuit niose, comparator metastability and other interference, the output of quantizer is first encoded with gray code and then converted to binary code. This high speed encoder is verified in the whole time-interleaved ADC with 0.18 Bi-CMOS technology, the whole ADC can achieve a SNR of 45 dB at the sampling rate of 5GHz and input frequency of 495MHz, meanwhile a bit error rate (BER) of less than 10-16 is ensured by this design.

The IC technology of adjustable delay is simply presented. Then aim at the engineering application forms a kind of segmented Digitally Controlled Delay Line (DCDL) which has overcame the tradeoff between adjustable delay resolution and dynamic range, benefited from small die area, high resolution and large adjustable range. Finally presented is the performance of the segmented DCDL which is fabricated by 0.18μm CMOS technology. From the test result, the DCDL’s resolution is 12ps and the dynamic range is 4ns.