This paper presents LCD-TV system with newly proposed 2.8Gbps/lane intra-panel interface for 3D TV applications. The proposed intra-panel interface transfers data in a point-to-point manner with embedded clock. Scrambling scheme was applied to stabilize loop bandwidth of bang-bang CDR, and to minimize EMI radiation. Timing controller (TCON) and source driver (SD) are implemented using 65nm/1.2V and 0.18um/1.8V CMOS processes, respectively. 2.8Gbps operation was verified by increasing horizontal blanking period while driving a 55-inch Full-HD LCD panel with 8-bit RGB and 120Hz frame rate. The proposed interface demonstrates the possibility of implementing an intrapanel system of 240Hz FHD LCD-TV for 3D displays with just one pair of differential data lines per SD. Number of data lines / SDTotal number of data lines AiPi [2] 8 48 CSDS [3] 6 36 CEDS [4] 4 24 Advanced-PPmL [5] 4 24 CalDriCon [6] 4 24 42.2 / J.-H. Kim 572 • SID 2012 DIGEST ISSN 0097-966X/12/4302-0572-$1.00

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A clock‐shared differential signaling (CSDS) scheme is newly proposed to support high resolution and large‐Size TFT‐LCDs with less than 3% overheads compared with transmitted data. CSDS adopts single‐level, multi‐dropped differential clocks which is shared among source driver ICs (CDs) and point‐to‐point connection for data lines. The protocol supporting CSDS makes the overhead of data transmission to be less than a few percent, which makes CSDS superior to other interfaces in terms of signal integrity, EMI, simple transmitter, and etc. It also supports flexible CD controls via just changing register values which are delivered by its protocol. And it is proved that CSDS supports 1.1Gbps per lane, which can cover next generation panels such as UD class.

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