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In this work we present a CMOS-compatible self-aligning process for the large-scale-integration of high-performance nanowire field effect transistors with well-saturated drain currents, steep subthreshold slopes at low drain voltage and a large on/off current ratio (>10(7)). The subthreshold swing is as small as 45 mV/dec, which is substantially beyond the thermodynamic limit (60 mV/dec) of conventional planar MOSFETs. These excellent device characteristics are achieved by using a clean integration process and a device structure that allows effective gate-channel-source coupling to tune the source/drain Schottky barriers at the nanoscale.

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We demonstrate a new postmetallization annealing and ultraviolet (UV) treatment process for reducing the dark current of image sensors. The new method utilizes a large amount of hydrogen in a plasma-silicon nitride film (p-SiNx) as a hydrogen diffusion source. Through charge pumping measurement, it is proved that this method effectively reduces the interface trap density of pixel transistors, thereby decreasing the dark current of image sensors. Although the postetch process for removing p-SiNx films induces plasma damage during the etch step, the damage can be effectively cured by the subsequent UV annealing.