Embedded die substrates (EDS) and embedded passives substrates (EPS) have been developed and promoted for many years already but still have to find their way into the market place. The adoption has been slow for several reasons: lack of a business model, design soft ware, test strategy and capability, standards and substrate yield. Printed wiring boards (PWB) have long adopted passives in their applications but they are typically formed passives i.e. capacitors, resistors and inductors formed during the board manufacturing process employing adapted materials to provide higher dielectric constants (D k ) or resistive values (□).Substrates are significantly smaller in area than PWBs and the materials still have rather low D k /□ values. Further the manufacturing processes involved do not afford tight tolerance values. Hence, substrates favor the use of discretes and known good (KGD) flip chip dies (FC). It seems that nearly every substrate manufacturer has developed they own methodology and employed their specific material set to develop this technology which circumvents standardization in the near term. A large volume adaptor will be required to drive standardization either thru a standards organization or de-facto thru large volume sourced from several suppliers. The yield situation of substrates can be addressed by design i.e. employ less aggressive designs which result in higher yields and avoid the costly scrap of KGDs. Of course substrate suppliers are not accustomed to handling die (die banks, electrostatic protection, thin die or small discrete handling, etc.) ASE is well positioned to deal with these issues being a substrate manufacturer as well as the largest assembly subcon.
The continued drive for miniaturization by mobile applications demands its toll also from packaging. Innovative packages are required to shrink volume and weight of packages. This has led to the development of single layer, coreless and embedded component substrates. The thinnest prepreg based substrate and concomitant package is a single layer substrate termed a-S3 ™ and can be as thin as 90 μ and 400 μ, respectively, with the appropriate mold cap. The manufacturing concept for a-S3 has inspired a new manufacturing concept for thin prepreg based coreless substrates with any number of layers. Layers two through seven have been demonstrated successfully. The practical layer count is limited only by yield and cycle time. The same concept has been extended also to embedding active die as well as passives, a-EASI™. The total package height here is governed by the thickness of the embedded elements. The simplest embedded substrate is a two layer substrate with a MOSFET die. The advantage is a very low profile power package with excellent electrical and thermal performance. The interconnections to the die/passives are formed by plated laser vias as is a common practice. Process flows and concepts will be introduced here. Thin substrates do pose many challenges during substrate manufacturing as well as during assembly. Some of the handling concepts will be elucidated. Sample pictures will be shown to demonstrate successful builds and some reliability data will be presented as well.
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