With the advent of bumped die new IC packages evolved: for low IO WLCSP (wafer level chip scale package), for high IO FC (flip chip) CBGA (ceramic ball grid array) and PBGA (plastic ball grid array). For low IO, protected CSP is an emerging and rapidly growing market. In 2020 the market exceeded $2B and is ramping to a forecast $2.5B by 2025.1 Initially WLCSP, also known as FI (fan in), packages were built on the wafer with no active side protection evolving to single sided protection from a package built on the wafer2 which transition to redistribution PSB (passivation stress buffer)3, PSBs were used on FC wafers for high IO BGA packages. These provided acceptable performance initially, however as devices became more complex and reliability requirements increased, these processes no longer provided the required reliability. To attain higher IO capability and better reliability performance evolved to CSP4 (non-WL) which allowed larger area for bump distribution and additional protection to the rest of the exposed die surfaces. Fully protected die CSP (without substrates or leadframes) was initially implemented with processes such as M-series utilizing a FO (fan out) process.5 To obtain higher reliability 6-sided die protection afforded by M-series type processes require die reconstitution, expensive tapes, molding, and other operations generally required in a FO process which can feasibly be eliminated in a WLCSP protected FI process. American Semiconductor's Semiconductor-on-Polymer™ (SoP™) 300mm FleX-TM WLCSP is an advanced packaging process optimized for protected fan-in. FleX-TM produces the thinnest and lowest cost protected FI the industry today. Protected FI process innovations can improve performance in power devices, RF switches, die stacking and thin board applications. This article includes background on the evolution of CSP and the comparison of SOTA (state of the art) FI processes including FleX-TM.

With the advent of bumped die, new IC packages evolved: for low IO WLCSP (wafer level chip scale package), for high IO FC (flip chip), CBGA (ceramic ball grid array), and PBGA (plastic ball grid array). For low IO, protected CSP is an emerging and rapidly growing market. In 2020 the market exceeded $2B and is ramping to a forecast $2.5B by 2025.1 Initially WLCSP, also known as FI (fan in), was built on the wafer with no active side protection, evolving to single sided protection from a package built on the wafer3 , which transitioned to redistribution PSB (passivation stress buffer)4 . PSBs were implemented in FC wafers for high IO BGA packages. These provided acceptable performance initially, however as devices became more complex and reliability requirements increased, these processes no longer provided the required reliability. To attain higher IO capability and better reliability, performance evolved to CSP5 (non-WL) which allowed larger area for bump distribution and additional protection to the rest of the exposed die surfaces. An example of fully protected die CSP (without substrates or leadframes) encapsulated in mold compound is M-series utilizing a FO (fan out) processes and eWLB.6,7 To obtain higher reliability 6-sided die protection afforded by FO processes require die reconstitution, expensive tapes, molding, and other operations which can feasibly be eliminated in a WLCSP protected FI process assuming full encapsulation can be attained on the original device wafer. American Semiconductor’s Semiconductor-on-Polymer (SoP) 300mm SoP-TM, a P-WLCSP process, is an advanced packaging process optimized for protected fan-in. SoP-TM produces the thinnest and lowest cost fully protected FI. Protected FI process innovations can improve performance in power devices, RF switches, die stacking and thin board applications. This paper includes background on the evolution of CSP, comparison of SOTA (state of the art) FI processes including SoP-TM and builds on low-cost wafer level adaptive process works and reliability data presented on the new SoP-TM process earlier this year.8,9 First article electrical reliability test data for P-WLCSP, adaptive processing of micro-bump pads, and potential applications in hybrid modules will be shown.

Cell phone boards are getting thinner. Labels and tags are getting smarter. Electronics is starting to bend. Consumers think thin is cool. Scaling thickness has and continues to be a key metric in packaging evolution. Chip Scale Packaging (CSP) defines the logical end of package scaling as package area and IC size converge. CSP, as well as the use of bare die, in Direct Chip Attach (DCA) integration pushes the limit of interconnect technology. CSP and implementation of direct interconnect attachment leads to the smallest packages possible. Technology and reliability advances in ultra-thin Semiconductor-on-Polymer (SoP) CSP and direct interconnect assembly is enabling flexible hybrid electronics and sensors today. SoP extends CSP package size reduction to less than 1.0X the die size. Semiconductor-on-Polymer (SoP) CSP results in ultra-thin semiconductor materials that are less than the thickness possible with bare die. SoP was initially introduced to the Flexible Electronics market; the technology has gained interest for conventional low profile, low-mid I/O, DCA type applications. Advanced SoP CSP is an ultra-thin packaging technology that is capable of complete die encapsulation using wafer level processing. Ultra-thin SoP CSP is new package technology. It is applied to fully characterized commercial devices, uses well know semiconductor materials and is generally “qualified by similarity” (QBS). Qualification for flexible applications supplement QBS with test procedures derived from established standards. The initial development of test methods and procedures was done with AFRL support in 2017. Initial reliability for the new flexibility tests will be presented. SoP CSP is undergoing further characterization for conventional applications. This includes testing that is typical of non-hermetic fully encapsulated parts. Flip-chip is the preferred method for assembly of SoP CSP. The ultra-thin package technology feature is fully utilized using Direct Interconnect (DI). Direct interconnect (DI) is defined as the die pad interconnect technology where the pad is connected directly to a board pad of equivalent size and spacing. Direct interconnect is common for low pad count devices such as RFID, NFC and other DCA applications. Direct interconnect is not typically considered for higher pin count devices…until now. This presentation shares the development of SoP CSP DI assembly that has progressed from 24 pin attachment to System-on-Chip assembly of DI pitch at <100um. The presentation also shows the technology roadmap for SoP CSP evolution. A case study of a SoP CSP application will be included with data from a fully assembled ultra-thin electronic system based on a SoP CSP SOC with total thickness less than 30um. The system includes on-board ultra-thin fully flexible sensors. A call to action will be made to embrace ultra-thin electronics. System Designers and IC Engineers will be encouraged to: BUILD! Create the vision for ultra-thin possibilities. Put electronics into places and things never before possible with, prototypes, testing, reporting, and introducing new thin concepts. Reliability Leaders will be encouraged to: TEST! Update test procedures and standards to include physical deformations and then report and challenge the industry to improve. Universities will be called to: CREATE! Generate new physics/models associated with deformations, develop interconnect innovations and advance new materials. In general, the presentation makes the case that hardware matters – Let's build some new technology.