We describe the optical design of a free-space interconnect system to be used for a 32 x 32 sorting system. The system uses 4f imaging relays to connect two hybrid optoelectronic-complementary metal-oxide semiconductor chips. These relays are used to implement a perfect-shuffle interconnect necessary for the sorting algorithm to be implemented. The relay lenses are also used with patterned mirrors and polarizing elements to combine read beams necessary for the optoelectronic chips. Issues relating to the basic system design and the detailed design of the lenses and optomechanics are given.

The algorithmic, electronic, and optical aspects of the implementation of a perfect-shuffle interconnected bitonic sorter are analyzed. The performance metrics such as the bit output data rate and the power consumption of the system are quantified. The sorting module is designed to demonstrate the parallel nonlocal interconnection of smart-pixel arrays and the use of optical-image control masks in a functioning information processor.

Free-space optical interconnects have been identified as a potentially important technology for future massively parallel-computing systems. The development of optoelectronic smart pixels based on InGaAs/AlGaAs multiple-quantum-well modulators and detectors flip-chip solder-bump bonded onto complementary-metal-oxide-semiconductor (CMOS) circuits and the design and construction of an experimental processor in which the devices are linked by free-space optical interconnects are described. For demonstrating the capabilities of the technology, a parallel data-sorting system has been identified as an effective demonstrator. By use of Batcher's bitonic sorting algorithm and exploitation of a perfect-shuffle optical interconnection, the system has the potential to perform a full sort on 1024, 16-bit words in less than 16 mus. We describe the design, testing, and characterization of the smart-pixel devices and free-space optical components. InGaAs-CMOS smart-pixel, chip-to-chip communication has been demonstrated at 50 Mbits/s. It is shown that the initial system specifications can be met by the component technologies.