Double patterning technology (DPT) is a promising technique that bridges the anticipated technology gap from the use of 193nm immersion to EUV for the half-pitch device node beyond 45nm. The intended mask pattern is formed by two independent patterning steps. Using DPT, there is no optical imaging correlation between the two separate patterning steps except for the impact from mask overlay. In each of the single exposure step, we can relax the dense design pattern pitches by decomposing them into two half-dense ones. This allows a higher k 1 imaging factor for each patterning step. With combined patterns, we can achieve overall k 1 factor that exceeds the conventional Rayleigh resolution limit. This paper addresses DPT application challenges with respect to both mask error factor (MEF) and 2D patterning. In our simulations using DPT with relaxed feature pitch for each exposure step, the MEF for the line/space is fairly manageable for 32nm half-pitch and below. The real challenge for the 32nm half-pitch and below with DPT is how to deal with the printing of small 2D features resulting from the many cutting sites due to feature decomposition. Each split of a dense pattern generates two difficult-to-print line-end type features with dimension less than one-fifth or onesixth of ArF wavelength. Worse, the proximity environment of the 2D cut features can then become quite complex. How to stitch them correctly back to the original target requires careful attention. Applying target bias can improve the printing performance in general. But using a model-based stitching error correction method seems to be a preferred solution.

The technical challenges in using F2 lithography for the 45nm node, along with the insurmountable difficulties in EUV lithography, has driven the semiconductor chipmaker into the low k 1 lithography era under the pressure of ever decreasing feature sizes. Extending lithography towards lower k 1 puts heavy demand on the resolution enhancement technique (RET), exposure tool, and the need for litho friendly design. Hyper numerical aperture (NA) exposure tools, immersion [1], and double exposure techniques (DET's) are the promising methods to extend lithography manufacturing to the 45nm node at k 1 factors below 0.3. Scattering bars (SB's) [2] have become an integral part of the lithography process as chipmakers move to production at ever lower k 1 factors. To achieve better critical dimension (CD) control, polarization is applied to enhance the image contrast in the preferential imaging orientation, which increases the risk of SB printability. The optimum SB width is approximately (0.20 ~ 0.25)*(λ/NA).[1] When the SB width becomes less than the exposure wavelength on the 4X mask, Kirchhoff's scalar theory under predicts the SB intensity. The optical weighting factor of the SB increases ( Figure 1b) and the SB's become more susceptible to printing. Meanwhile, under hyper NA condition's, the effectiveness of "sub-resolution" SB's is significantly diminished. A full-sized scattering bars (FSB) scheme becomes necessary. Double exposure methods, such as using ternary 6% attenuated PSM (attPSM) for DDL, are good imaging solutions that can reach and likely go beyond the 45nm node. Today DDL, using binary chrome masks, is capable of printing 65 nm device patterns. [3,4,5] In this work, we investigate the use of DET with 6% attPSM masks to target 45nm node device. The SB scalability and printability issues can be taken cared of by using "mutual trimming", i.e., with the combined energy from the two exposures. In this study, we share our findings of using DET to pattern a 45nm node device design with polarization and immersion. We also explore other double patterning methods which in addition to having two exposures, incorporates double coat/developing/etch processing to break the 0.25 k 1 barrier.

Extending ArF lithography to the 45nm node at a lower k 1 puts a heavy demand on resolution enhancement techniques (RETs), exposure tools, and lithography friendly design. Hyper numerical aperture (NA) exposure tools, immersion [1], and double exposure techniques (DETs) are promising methods to extend lithography manufacturing to the 45nm node at k 1 factors around 0.3. Double dipole lithography (DDL) is becoming a popular RET candidate for foundries and memory makers to pattern the poly gate active layer [2, 3, 4]. Double exposure method or double pattern technique (DPT), [5,6,7] using ternary 6% attenuated PSM (attPSM) is a good imaging solution that can reach and likely go beyond the 45nm node. In this work, back end of the line (BEOL) metal like test structures were used for developing a model-based dark field DDL method. We share our findings of using DDL for patterning 45nm node trench structures with binary intensity mask (BIM) on a dry high NA ArF scanner.

Fostered by continued advancements in the field of optical extension technologies, optical lithography continues to extend far beyond what was thought possible only a few years ago. The application of chromeless phase lithography (CPL), or ''100% transmission PSM,'' has been used to demonstrate the potential for optical lithography to image features as small as one-quarter of the exposure wavelength at pitches that are below the exposure wavelength. The ability to print 70 nm lines through pitch using a 248 nm, 0.70 numerical aperture (NA) wafer scanner, QUASAR off-axis illumination, and a chromeless mask (CLM) has been demonstrated by Chen et al. [Chen et al., Proc. SPIE. 4346, 515-533 (2001)]. However, it was confirmed by Chen et al. that imaging complex two-dimensional (2-D) structures with high transmission CLM reticles involves very strong optical proximity effects. The need to use high NA wafer steppers with off-axis illumination in order to apply chromeless phase lithography exacerbates these effects. This phenomenon is further magnified and the interactions become more complex as the pitch between 2-D structures is decreased. The nature of the proximity effects observed with chromeless phase lithography and the means by which to correct for them using various optical proximity correction (OPC) methods are described and explained. Patterns that represent real device-like structures are used to demonstrate that data processing algorithms are feasible and can correct the induced proximity effects and thus make it possible to incorporate CPL technology for low-k 1 production lithography.

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