This paper presents a power-and area-efficient 24-way time-interleaved SAR ADC designed in 65nm CMOS. At 2.8GS/s sampling rate the ADC consumes 44.6mW of power from a 1.2V supply while achieving peak SNDR of 50.9dB and retaining SNDR higher than 48.2dB across the entire first Nyquist zone. Introduction High demand for low-power ADCs with sampling frequencies of 2-3GHz and effective resolution of 7-8 bits is driven by applications such as direct-sampling receivers in cable modems [1] and digital baseband implementations of 60GHz communication systems [2]. The state-of-the-art solution [1] consumes 0.48W of power and occupies an active area of 5.1mm 2 . In this work both the area and power consumption of the ADC are each reduced by an order of magnitude. The main enabling technique for this improvement is miniaturization of the capacitors in the capacitive DAC of the interleaved SAR ADCs to the point where the ADC operates in a thermal noise limited regime. The minimum employed capacitor size is 50aF, ten times lower than previously reported [3] and well below the matching requirements, for a total sampling capacitance of 50fF and quantization noise at 10-bit level. This leads to a small area per channel and consequently allows for the distribution of input, clock, and reference signals without the need for power-hungry buffering. To be able to digitally correct static nonlinearities due to capacitor mismatches, a reduced radix of 1.85 is used in the capacitive DACs. A background least-mean-square (LMS) calibration technique that corrects static nonlinearities, offset, gain and timing mismatches has been implemented on the chip. Chip Architecture A high-level block diagram of the implemented ADC is shown in Fig. 1. It consists of M=24 time-interleaved channels, with two additional channels used for calibration. Each channel is split in two parts: analog (SARx_A, which also includes SAR logic), and digital (SARx_D). The digital part forms the final output by summing the weighted output bits from the analog part and the digital representation of the channel offsets. The values of digital weight coefficients and offsets are adaptive and are iteratively calculated in the 'linearity LMS' block. The timing LMS calculates timing mismatches and tunes the delay elements, Δt.Two modes of conversion, named the direct and the reverse switching, can be selected in all channels. In the direct switching mode, after sampling the input signal onto all capacitors in the DAC, the MSB capacitor is connected to the positive reference V rp , while all other capacitors are connected to the negative reference V rn as shown in Fig. 2.a. In the reverse switching, the MSB capacitor is connected to V rn and all others to V rp (Fig. 2.c). After the first bit is resolved, the MSB capacitor is connected to V rp if the resolved bit is '1' or to V rn if the resolved bit is '0', both in direct and reverse switching (Fig. 2.b and 2.d). All other bits are resolved in a similar way. These two modes of operation have transfer characteristics t...

This paper presents a power-and area-efficient 24-way time-interleaved SAR ADC designed in 65nm CMOS. At 2.8GS/s sampling rate the ADC consumes 44.6mW of power from a 1.2V supply while achieving peak SNDR of 50.9dB and retaining SNDR higher than 48.2dB across the entire first Nyquist zone. Introduction High demand for low-power ADCs with sampling frequencies of 2-3GHz and effective resolution of 7-8 bits is driven by applications such as direct-sampling receivers in cable modems [1] and digital baseband implementations of 60GHz communication systems [2]. The state-of-the-art solution [1] consumes 0.48W of power and occupies an active area of 5.1mm 2 . In this work both the area and power consumption of the ADC are each reduced by an order of magnitude. The main enabling technique for this improvement is miniaturization of the capacitors in the capacitive DAC of the interleaved SAR ADCs to the point where the ADC operates in a thermal noise limited regime. The minimum employed capacitor size is 50aF, ten times lower than previously reported [3] and well below the matching requirements, for a total sampling capacitance of 50fF and quantization noise at 10-bit level. This leads to a small area per channel and consequently allows for the distribution of input, clock, and reference signals without the need for power-hungry buffering. To be able to digitally correct static nonlinearities due to capacitor mismatches, a reduced radix of 1.85 is used in the capacitive DACs. A background least-mean-square (LMS) calibration technique that corrects static nonlinearities, offset, gain and timing mismatches has been implemented on the chip. Chip Architecture A high-level block diagram of the implemented ADC is shown in Fig. 1. It consists of M=24 time-interleaved channels, with two additional channels used for calibration. Each channel is split in two parts: analog (SARx_A, which also includes SAR logic), and digital (SARx_D). The digital part forms the final output by summing the weighted output bits from the analog part and the digital representation of the channel offsets. The values of digital weight coefficients and offsets are adaptive and are iteratively calculated in the 'linearity LMS' block. The timing LMS calculates timing mismatches and tunes the delay elements, Δt.Two modes of conversion, named the direct and the reverse switching, can be selected in all channels. In the direct switching mode, after sampling the input signal onto all capacitors in the DAC, the MSB capacitor is connected to the positive reference V rp , while all other capacitors are connected to the negative reference V rn as shown in Fig. 2.a. In the reverse switching, the MSB capacitor is connected to V rn and all others to V rp (Fig. 2.c). After the first bit is resolved, the MSB capacitor is connected to V rp if the resolved bit is '1' or to V rn if the resolved bit is '0', both in direct and reverse switching (Fig. 2.b and 2.d). All other bits are resolved in a similar way. These two modes of operation have transfer characteristics t...

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The high-speed and high-resolution ADC is a key enabler for many future wireless communications systems. The digital background calibration technique can be used to reduce the total power consumption by enhancing the linearity without using high-gain amplifiers. One of the main practical constraints in the wireless applications is a short time available for calibration. This paper proposes a novel fast calibration method of pipelined ADCs, suitable for wireless communications applications, where a sufficiently high resolution can be achieved without requiring any calibration period.