A quantitative analysis of the thermoelectric power measurements on composite AlGe films A quantitative comparison between theory and experiment is presented for the thermoelectric power of n-type Si at low temperatures, where crystal boundary scattering of phonons is predominant. The expression for the Seebeck coefficient is obtained by simultaneously solving the coupled Boltzmann equations for electrons and phonons. The thermoelectric power is measured from samples of two different donor concentrations (N D = 8 X 10 14 em 3 and 7 X 10 15 cm -3 ) at temperatures ranging from 25 to 200 K, where the thickness is varied by etching the samples (370-73 p,m). The phonon mean free path for crystal boundary scattering, determined from experimental thermopower, agrees well with that gained from the theory of thermal conductivity corrected for the phonon velocities of interest. An additional measurement of the thermal conductivity yields the mean free path for phonon-phonon scattering, which is about two orders of magnitude less than that obtained from thermopower. This difference confirms the influence of the different parts ofthe phonon spectrum involved in the calculation of the appropriate transport parameters.

We describe the challenges of migrating the Cell Broadband Engine TM (Cell BE) [1-2] design from a 65nm SOI [3] to a 45nm twin-well CMOS technology on SOI with low-κ dielectric (κ = 2.4) and 10 copper metal layers [4]. The technology offers dual-gateoxide thicknesses of 1.16nm and 2.5nm for 1.0V and 1.5V nominal power supply, respectively. Thicker oxide devices are used in analog circuits. To guarantee the proper operation of existing gaming software, the exact cycle-by-cycle machine behavior, including operating frequency, must be preserved. We set the focus of design migration to four goals: 1) automated design migration where possible, 2) 30% power reduction, 3) 30% area reduction, and 4) design for manufacturability (DFM) improvement. With the design rules across technologies being relatively compatible, we take advantage of automated migration for the bulk of Cell BE circuit blocks. Circuits are manually fine tuned for timing, noise tolerance, and design robustness after the initial automatic migration. We take a different approach with memory and analog circuits. Analog circuits do not scale well due to the required area for decoupling capacitance. The I/O area, especially the area for C4 bumps, dictates chip dimensions since the same number of I/O signals is required and the C4 pitch does not scale from the previous technology.Since digital circuits occupy the bulk of chip area, it is crucial to migrate them effectively. The original digital circuits in 65nm consist of 3 types of components: parameterized cells, common leaf cells (flip-flop and local clock buffer), and custom cells. The migration of parameterized cells is done through software. A tool called Migration Assistant Shape Handler (MASH) [5] is applied to the common leaf cells first. MASH first shrinks the shapes according to the scale factor between technologies. Second, MASH corrects as many design rule violations in 45nm as possible with minimum layout perturbations and the remaining violations are repaired manually. The pin locations for these cells are fixed and scaled only in size. Metal blockage changes are minimized to reduce the effect on higher design levels. Hierarchical migration is performed in 2 phases. The first phase includes placing scaled leaf cells at scaled coordinates and scaling any remaining shapes. The second phase applies MASH to remove design rule violations. Using this design migration methodology, we shrink the chip size by 34% with respect to 65nm. Figure 4.3.1 shows dimensions of Cell BE and its major partitions in 3 technologies.We take advantage of the automated approach as much as possible by applying it to smaller memory array blocks and then tuning circuits manually. As the SRAM cell size (0.404mm 2 ) shrinks in 45nm from 65nm (0.7mm 2 ), we address the cell stability concern due to process variability [6] by using a separate array power supply (V CS ). Lowering the main power supply (V DD ) is critical for reducing the chip power consumption. However, we cannot lower V CS by the same amount as V DD due to SRAM...

This paper reviews the design challenges that current and future processors must face with stringent power limits and high frequency targets, and the design methods required to address the continuing system integration trends. This paper then describes the implementation of a first-generation CELL processor and the design methods used to overcome the above challenges. A CELL Processor consists of a 64 bit Power Architecture processor coupled with multiple synergistic processors, a flexible IO interface, and a memory interface controller that supports multiple operating systems including Linux. This multi-core SoC, implemented in 90nm SOI technology, achieved a high clock rate by maximizing custom circuit design while maintaining reasonable complexity through design modularity and reuse.

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