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A nickel silicide polysilicon eFUSE provides a reliable, highly resistive programmed fuse while enabling reconfiguration of the VLSI functional features in traditional eFUSE applications with zero addition to the manufacturing process. The eFUSE has a history of wide use in embedded systems [1,2]. In previous work, a 65nm macro employed an array structure which improved areaper-bit by >10× and reduced programming time by >90% [3] over the traditional design [4]. For 45nm and beyond, it is necessary to have a design that has a V t -mismatch-immune sense scheme, provides a sufficient voltage window for field-programming, and has in-hardware testability features for commercial design. This paper describes a second-generation one-time programmable read-only memory (OTPROM) that provides these features through a balanced bitline, resistor pull-up, differential sense amp with a programmable reference.The OTPROM is organized into a 2D eFUSE array structure. The 4096 bits are arranged as 64 wordlines (WL) × 64 bitlines (BL). Each column consists of 64 fuse cells, each composed of one eFUSE and a selection NMOS transistor (3.6μm 2 /fuse). In addition, each array column has one differential sense amplifier with programmable reference circuitry and one fuse-programming structure with a power sense amp level-shifter to eliminate leakage paths. The array is also supported by a WL decoder and a reference decoder.The programming path selects a column putting VPRG (~1.5V) on the BL. One WL is decoded, selecting each of the fuse-cell NMOS devices, ensuring that a single fuse cell receives the programming current. A power sense amp level-shifter, shown in Fig. 22.4.1, selects the greater of VPRG or VDD to drive the column select devices in order to prevent BL leakage paths when in programming, sense, or resistance-measurement mode.The sense path uses a differential sense amplifier, Fig. 22.4.2, with resistor pull-up devices, balanced BLs, a PMOS header, body-contacted devices, stacked transmission gates, stacked PMOS devices, and a programmable reference. By using a PMOS header device, a three-stage amplification is achieved, Fig. 22.4.3. For a sense operation, one out of 64 WLs selects 64 bits of a row. Also, a reference resistor is selected for the opposite side of each sense amplifier. A voltage divider generates a signal for each side of the sense amp between the pull-up resistor and the blown/unblown fuse or the pull-up resistor and the reference resistor. The second stage activates the PMOS header generating more differential. The third stage activates the NMOS footer and isolates the sense amp from the BLs, pulling the cross-couple nodes to rail.In small-geometry processing, V t variation between paired devices reduces the trip-point predictability of differential sense amps. This effect causes the trip-point resistance of the sense amp to vary statistically between a maximum and minimum resistance creating a gray zone of uncertainty where a sense amp cannot be guaranteed to predictably sense over a large sample. Iterative ...

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This paper describes the technology and semi-custom design aspects of the AS/400 Power€" chip set. In order to meet the growing demand for AS/400 system performance, a 6ns cycle time was specified. This requirement, coupled with the desire for a short development cycle, drove the chip team to choose a semi-custom design style utilizing a mature BICMOS technology. Three semi-custom chips and one ASIC were designed and packaged in a multi-chip, high performance package to form the processor engine. the dataflow logic. These additional flexibilities, weaved into our existing ASIC process, formed the basis for our "structured custom" methodology. 3 semi-custom chips were developed: Processor Unit (PU) Floating Point Unit (FPU) Mainstore Contol Unit (MSCU) Please reference Figure 1 and 2. .O Introduction 2.0 Technology Selection andHistorically, the CPU designed for our AS/400 systems has been implemented using CMOS and (more recently) BICMOS semiconductor technologies. On the high-end of the AS/400 family the processor strategy has traditionally been a multi-chip implementation based on a small number of CMOS/BICMOS chips that followed a pure ASIC design approach. In order to meet cycle time goals on areduced schedule, a semicustom design methodology was chosen using a mature 0.8micron BiCMOS technology. Semi-custom design techniques were necessary to obtain the density and perform boost over what our traditional ASIC process could deliver. SpecificationsThe technology chosen for the AS/400 chip set based on a PowerPP architecture was a 0.8 micron BiCMOS process. The primary reason for this choice was the availability of a technology that could give us the performance required while being mature enough to fit our schedule requirements. Major drawbacks were 1) cost (ie. BIC-MOS > CMOS) and 2) limited manufacturing capability to build large die sizes.The technology specifications are as follows:0.8 micron lithography 5 Levels of Metal (4 wiring planes, 1 power distribution plane.A design methodology was adopted that allowed the designers the flexilibility to build specific custom library elements as well as custom arravs. C4 "flip chip" YO'S lo00 signal I/O, 1650 Power I/O . 2 m s typical 2w NAND delay This expanded library, was then coupled with a structured global layout approach. A physical hierarchy was established which made use of a bitstack layout approach for 1063-6404/94 $4.00 0 1994 IEEE 197