AS/400 PowerPC compatible semi-custom technology

Abstract

This paper describes the technology and semi-custom design aspects of the AS/400 Power€" chip set. In order to meet the growing demand for AS/400 system performance, a 6ns cycle time was specified. This requirement, coupled with the desire for a short development cycle, drove the chip team to choose a semi-custom design style utilizing a mature BICMOS technology. Three semi-custom chips and one ASIC were designed and packaged in a multi-chip, high performance package to form the processor engine. the dataflow logic. These additional flexibilities, weaved into our existing ASIC process, formed the basis for our "structured custom" methodology. 3 semi-custom chips were developed: Processor Unit (PU) Floating Point Unit (FPU) Mainstore Contol Unit (MSCU) Please reference Figure 1 and 2. .O Introduction 2.0 Technology Selection andHistorically, the CPU designed for our AS/400 systems has been implemented using CMOS and (more recently) BICMOS semiconductor technologies. On the high-end of the AS/400 family the processor strategy has traditionally been a multi-chip implementation based on a small number of CMOS/BICMOS chips that followed a pure ASIC design approach. In order to meet cycle time goals on areduced schedule, a semicustom design methodology was chosen using a mature 0.8micron BiCMOS technology. Semi-custom design techniques were necessary to obtain the density and perform boost over what our traditional ASIC process could deliver. SpecificationsThe technology chosen for the AS/400 chip set based on a PowerPP architecture was a 0.8 micron BiCMOS process. The primary reason for this choice was the availability of a technology that could give us the performance required while being mature enough to fit our schedule requirements. Major drawbacks were 1) cost (ie. BIC-MOS > CMOS) and 2) limited manufacturing capability to build large die sizes.The technology specifications are as follows:0.8 micron lithography 5 Levels of Metal (4 wiring planes, 1 power distribution plane.A design methodology was adopted that allowed the designers the flexilibility to build specific custom library elements as well as custom arravs. C4 "flip chip" YO'S lo00 signal I/O, 1650 Power I/O . 2 m s typical 2w NAND delay This expanded library, was then coupled with a structured global layout approach. A physical hierarchy was established which made use of a bitstack layout approach for 1063-6404/94 $4.00 0 1994 IEEE 197