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As the interconnect RC delay becomes a dominant factor in determining the overall circuit performance, the advantages of Cu and low k materials become more remarkable. The introduction of new materials is driving significant research of the impact of these materials on the reliability. Active investigation is focus on the impact of back end of line (BEOL) processing on Cu/low k reliability. Until now, the investigation mainly focuses on the EM and SM, etc. In this paper, inter layer dielectric (ILD) characteristic ramped voltage breakdown (VBD) of multiplayer Cu/SiOC interconnect was investigated. It was found the breakdown performance is highly process-related. Some process/integration changes have significant influence on VBD performance, such as some specific treatment to Cu surface, application of capping layer, and modified deposition process of etch stop layer (ESL), etc. ExperimentalIn this work, PECVD nitrogen-doped silicon carbide (SiC:N, k=5.1) and SiOC low k material (k=3.0) were used as ESL and inter-metal dielectrics for 90 nm technology node. A simple via first architecture was employed. In this integration scheme, after via etching/ashing and clean, trench was patterned and etched. It was followed by the traditional PVD, ECP and CMP. Fig.1 shows the schematic of dual damascene structure of Cu/low k Integration. Figure 1. Schematic of Dual Damascene Structure of Cu/low k Integration.IMD Inter -metal M1 Via

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Recently, it was found that for 65 nm logic device the VBD for SiN will decrease dramatically (from about 60 V to below 30-40 V if the queue is longer than eight hours) when the queue time after Cu CMP (prior to damascene SiN deposition) is longer than two hours. The problem happened most at SiN and BD I interface (Metal layer 5 with the same design rule of line spacing of Metal layer 2). Such a problem makes the BEOL production extremely difficult. To overcome this major challenge for SiN, we have analyzed the various kinds of potential root causes and showed that the change of Cu oxidation post Cu CMP is the real root cause. We have developed a series of new pre-clean recipes and tested most of them at customer site with customer's device wafers together with CVD division at the 300 mm fab of Applied Materials in USA. In this paper, we will discuss the potential mechanisms of time dependant VBD degradation and the practical solution to this problem.